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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	15d ago
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package.json	tps60133pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	9d ago
page.json	tps60133pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	9d ago
README.md	Publish 0.1.0 · Ray	15d ago
tps60133pwpr-etched.glb	tps60133pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	9d ago
tps60133pwpr-etched.step	tps60133pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	9d ago
tps60133pwpr-hero.glb	tps60133pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	9d ago
tps60133pwpr-hero.overlay.json	tps60133pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray	9d ago
tps60133pwpr.glb	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	9d ago
tps60133pwpr.kicad_mod	Publish 0.1.0 · Ray	15d ago
tps60133pwpr.kicad_sym	Publish 0.1.0 · Ray	15d ago
tps60133pwpr.lbr	Publish 0.1.0 · Ray	15d ago
tps60133pwpr.step	plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray	9d ago

TPS60133PWPR

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS60133PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Analog ground for the internal reference and control circuitry, to be connected to the PGND pins through a short trace.
2	GND	power_in	Analog ground for the internal reference and control circuitry, to be connected to the PGND pins through a short trace.
3	ENABLE	input	Enable input that must be connected to IN for normal operation; a logic low turns the device off, reduces supply current to 0.05 µA, and disconnects the output from the input.
4	FB	input	Feedback input to be connected to OUT as close to the load as possible, using an on-chip resistive divider that matches the internal 1.21-V reference.
5	OUT	power_out	Regulated 5-V power output to be connected together with OUT pin 16 through a short trace and bypassed to GND with the output filter capacitor CO.
6	C1+	passive	Positive pin of the flying capacitor C1 of the charge pump.
7	IN	power_in	Supply input, bypassed to PGND with a capacitor of half the output capacitance and connected together with IN pin 14 through a short trace; operating input range is 2.7 V to 5.4 V.
8	C1-	passive	Negative pin of the flying capacitor C1 of the charge pump.
9	PGND	power_in	Power ground carrying the charge-pump current; all PGND pins must be connected together.
10	PGND	power_in	Power ground carrying the charge-pump current; all PGND pins must be connected together.
11	PGND	power_in	Power ground carrying the charge-pump current; all PGND pins must be connected together.
12	PGND	power_in	Power ground carrying the charge-pump current; all PGND pins must be connected together.
13	C2-	passive	Negative pin of the flying capacitor C2 of the charge pump.
14	IN	power_in	Supply input, bypassed to PGND with a capacitor of half the output capacitance and connected together with IN pin 7 through a short trace; operating input range is 2.7 V to 5.4 V.
15	C2+	passive	Positive pin of the flying capacitor C2 of the charge pump.
16	OUT	power_out	Regulated 5-V power output to be connected together with OUT pin 5 through a short trace and bypassed to GND with the output filter capacitor CO.
17	LBO/PG	output	On the TPS60133 this is the Power Good open-drain output, which can sink 1 mA and should use a 100-kΩ to 1-MΩ pullup to OUT, or be left unconnected if unused.
18	LBI/NC	unconnected	On the TPS60133 this pin is not connected; the low-battery detector input function applies only to the TPS60130 and TPS60132.
19	GND	power_in	Analog ground for the internal reference and control circuitry, to be connected to the PGND pins through a short trace.
20	GND	power_in	Analog ground for the internal reference and control circuitry, to be connected to the PGND pins through a short trace.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-20-EP
Category	Power Supply Chip
Pins	21

CAD (KiCad official)

Symbol: TPS60133PWPR
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: tps60133pwpr-etched.step / tps60133pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps60133pwpr.step / tps60133pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (35 pp, sha256 d141bc3562ef13fe, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF