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TPS60130PWPR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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package.json tps60130pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
page.json tps60130pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
README.md tps60130pwpr: specified limits as data (metadata.characteristics, 28 rows from the datasheet) · Ray 11d ago
tps60130pwpr-etched.glb tps60130pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
tps60130pwpr-etched.step tps60130pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
tps60130pwpr-hero.glb tps60130pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
tps60130pwpr-hero.overlay.json tps60130pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
tps60130pwpr.glb plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 9d ago
tps60130pwpr.kicad_mod Publish 0.1.0 · Ray 15d ago
tps60130pwpr.kicad_sym Publish 0.1.0 · Ray 15d ago
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tps60130pwpr.step plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 9d ago

TPS60130PWPR

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS60130PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Analog ground for the internal reference and control circuitry; connect to the PGND pins through a short trace.
2 GND power_in Analog ground for the internal reference and control circuitry; connect to the PGND pins through a short trace.
3 ENABLE input Enable input; connect to IN for normal operation, and when driven logic low the device turns off, supply current falls to 0.05 µA and the output is disconnected from the input.
4 FB input Feedback input; connect to OUT as close to the load as possible for best regulation, with an on-chip resistive divider matching the internal 1.21-V reference.
5 OUT power_out Regulated 5-V power output; connect both OUT pins through a short trace and bypass OUT to GND with the output filter capacitor CO.
6 C1+ passive Positive terminal of flying capacitor C1.
7 IN power_in Supply input; bypass to PGND with a capacitor having half the capacitance of the output capacitor and connect both IN pins together through a short trace.
8 C1- passive Negative terminal of flying capacitor C1.
9 PGND power_in Power ground carrying the charge-pump current; connect all PGND pins together.
10 PGND power_in Power ground carrying the charge-pump current; connect all PGND pins together.
11 PGND power_in Power ground carrying the charge-pump current; connect all PGND pins together.
12 PGND power_in Power ground carrying the charge-pump current; connect all PGND pins together.
13 C2- passive Negative terminal of flying capacitor C2.
14 IN power_in Supply input; bypass to PGND with a capacitor having half the capacitance of the output capacitor and connect both IN pins together through a short trace.
15 C2+ passive Positive terminal of flying capacitor C2.
16 OUT power_out Regulated 5-V power output; connect both OUT pins through a short trace and bypass OUT to GND with the output filter capacitor CO.
17 LBO/PG output Open-drain low battery detector output (TPS60130 and TPS60132) or Power Good output (TPS60131 and TPS60133), able to sink 1 mA, with a 100-kΩ to 1-MΩ pullup to OUT recommended and left unconnected if unused.
18 LBI/NC input Low battery detector input on TPS60130 and TPS60132 only, compared to the internal 1.21-V reference and tied to ground if unused; not connected on TPS60131 and TPS60133.
19 GND power_in Analog ground for the internal reference and control circuitry; connect to the PGND pins through a short trace.
20 GND power_in Analog ground for the internal reference and control circuitry; connect to the PGND pins through a short trace.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage (IN, OUT, ENABLE, FB, LBI, LBO/PG) VI -0.3 5.5 V 5
Differential input voltage C1+, C2+ to GND VID -0.3 V C1+, C2+ to GND; printed max VO + 0.3 5
Differential input voltage C1-, C2- to GND VID -0.3 V C1-, C2- to GND; printed max VI + 0.3 5
Continuous output current 400 mA TPS60130 and TPS60131 5
Maximum junction temperature 150 °C 5
Storage temperature Tstg 150 °C 5
Input voltage VI 2.7 5.4 V 5
Output current IO 300 mA TPS60130 and TPS60131 5
Operating junction temperature TJ 125 °C 5
Junction-to-ambient thermal resistance RθJA 178.75 °C/W PWP (HTSSOP) 20 pins 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.5 °C/W PWP (HTSSOP) 20 pins 5
Input voltage VI 2.7 5.4 V 6
Input undervoltage lockout threshold V(UVLO) 1.6 1.8 V TC = 25°C 6
Maximum output current IO(MAX) 300 mA TPS60130 and TPS60131 6
Output voltage VO 4.8 5.2 V 2.7 V < VI < 3 V, 0 < IO < IO(MAX)/2, TC = 0°C to 70°C 6
Output voltage VO 4.8 5.25 V 5 V < VI < 5.4 V, 0 < IO < IO(MAX) 6
Output leakage current Ilkg(OUT) 1 µA VI = 3.6 V, V(ENABLE) = 0 V 6
Quiescent current (no-load input current) IQ 60 100 µA VI = 3.6 V 6
Shutdown supply current IQ(SDN) 0.05 1 µA VI = 3.6 V, V(ENABLE) = 0 V 6
Internal switching frequency fOSC(INT) 210 320 450 kHz 6
Enable input leakage current Ilkg(ENABLE) 0.01 0.1 µA V(ENABLE) = VGND or VI 6
Output load regulation 0.002 % mA VI = 3.8 V, 1 mA < IO(maximum), TC = 25°C 6
Output line regulation 0.2 % V 3 V < VI < 5 V, IO = 150 mA, TC = 25°C 6
Short-circuit current limit 115 mA VI = 3.6 V, VO = 0 V, TC = 25°C 6
LBI trip voltage (TPS60130 and TPS60132) V(LBITRIP) 1.15 1.21 1.27 V VI = 2.7 V to 3.3 V, hysteresis 0.8% for rising LBI, TC = 0°C to 70°C 6
LBI input current (TPS60130 and TPS60132) II(LBI) 100 nA V(LBI) = 1.3 V 6
LBO output voltage low (TPS60130 and TPS60132) VO(LBO) 0.4 V V(LBI) = 0 V, I(LBO)(SINK) = 1 mA 6
LBO leakage current (TPS60130 and TPS60132) Ilkg(LBO) 0.01 0.1 µA V(LBI) = 1.3 V, V(LBO) = 5 V 6

CAD (KiCad official)

  • Symbol: TPS60130PWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps60130pwpr-etched.step / tps60130pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps60130pwpr.step / tps60130pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 d141bc3562ef13fe, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF