TPS60111PWP

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS60111PWP from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Analog ground for internal reference and control circuitry; connect to PGND through a short trace.
2	SYNC	input	Clock synchronization selection; connect to GND for internal clock or to IN for external synchronization.
3	ENABLE	input	Enable input; device enters shutdown mode (0.05 µA max) when low and output disconnects from input.
4	FB	input	Feedback input for 5-V regulation via on-chip 1.22-V reference divider; connect close to load for best regulation.
5	OUT	power_out	Regulated 5-V ±4% output at 150 mA maximum; bypass to GND with output filter capacitor.
6	C1+	output	Positive terminal of charge-pump capacitor C1F; actively driven flying capacitor node.
7	IN	power_in	Supply input in 2.7-V to 5.4-V range; bypass to GND with (CO/2) µF capacitor and connect both INs through short trace.
8	C1−	output	Negative terminal of charge-pump capacitor C1F; actively driven flying capacitor node.
9	PGND	power_in	Power ground for charge-pump current flow; connect all PGND pins together.
10	PGND	power_in	Power ground for charge-pump current flow; connect all PGND pins together.
11	PGND	power_in	Power ground for charge-pump current flow; connect all PGND pins together.
12	PGND	power_in	Power ground for charge-pump current flow; connect all PGND pins together.
13	C2−	output	Negative terminal of charge-pump capacitor C2F; actively driven flying capacitor node.
14	IN	power_in	Supply input in 2.7-V to 5.4-V range; bypass to GND with (CO/2) µF capacitor and connect both INs through short trace.
15	C2+	output	Positive terminal of charge-pump capacitor C2F; actively driven flying capacitor node.
16	OUT	power_out	Regulated 5-V ±4% output at 150 mA maximum; connect both OUTs through short trace.
17	SKIP	input	Mode selection input; low for constant-frequency mode (minimized ripple), high for pulse-skip mode (low quiescent current).
18	COM	input	Mode selection input; low for push-pull mode (minimized ripple), high/IN for single-ended mode (fewer components).
19	CLK	input	External clock signal input (400-800 kHz range) when SYNC is high; connect to GND for internal 300-kHz clock.
20	GND	power_in	Analog ground for internal reference and control circuitry; connect to PGND through a short trace.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-20-EP
Category	Power Supply Chip
Pins	21

CAD (KiCad official)

Symbol: TPS60111PWP
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: tps60111pwp-etched.step / tps60111pwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps60111pwp.step / tps60111pwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (26 pp, sha256 f590960ada84532a, retrieved 2026-10-07, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPS60111PWP

**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP

TPS60111PWP from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Analog ground for internal reference and control circuitry; connect to PGND through a short trace. |
| 2 | SYNC | input | Clock synchronization selection; connect to GND for internal clock or to IN for external synchronization. |
| 3 | ENABLE | input | Enable input; device enters shutdown mode (0.05 µA max) when low and output disconnects from input. |
| 4 | FB | input | Feedback input for 5-V regulation via on-chip 1.22-V reference divider; connect close to load for best regulation. |
| 5 | OUT | power_out | Regulated 5-V ±4% output at 150 mA maximum; bypass to GND with output filter capacitor. |
| 6 | C1+ | output | Positive terminal of charge-pump capacitor C1F; actively driven flying capacitor node. |
| 7 | IN | power_in | Supply input in 2.7-V to 5.4-V range; bypass to GND with (CO/2) µF capacitor and connect both INs through short trace. |
| 8 | C1− | output | Negative terminal of charge-pump capacitor C1F; actively driven flying capacitor node. |
| 9 | PGND | power_in | Power ground for charge-pump current flow; connect all PGND pins together. |
| 10 | PGND | power_in | Power ground for charge-pump current flow; connect all PGND pins together. |
| 11 | PGND | power_in | Power ground for charge-pump current flow; connect all PGND pins together. |
| 12 | PGND | power_in | Power ground for charge-pump current flow; connect all PGND pins together. |
| 13 | C2− | output | Negative terminal of charge-pump capacitor C2F; actively driven flying capacitor node. |
| 14 | IN | power_in | Supply input in 2.7-V to 5.4-V range; bypass to GND with (CO/2) µF capacitor and connect both INs through short trace. |
| 15 | C2+ | output | Positive terminal of charge-pump capacitor C2F; actively driven flying capacitor node. |
| 16 | OUT | power_out | Regulated 5-V ±4% output at 150 mA maximum; connect both OUTs through short trace. |
| 17 | SKIP | input | Mode selection input; low for constant-frequency mode (minimized ripple), high for pulse-skip mode (low quiescent current). |
| 18 | COM | input | Mode selection input; low for push-pull mode (minimized ripple), high/IN for single-ended mode (fewer components). |
| 19 | CLK | input | External clock signal input (400-800 kHz range) when SYNC is high; connect to GND for internal 300-kHz clock. |
| 20 | GND | power_in | Analog ground for internal reference and control circuitry; connect to PGND through a short trace. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |

## CAD (KiCad official)

- Symbol: `TPS60111PWP`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps60111pwp-etched.step` / `tps60111pwp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps60111pwp.step` / `tps60111pwp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps60111) (26 pp, sha256 `f590960ada84532a`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps60111pwp-datasheet.pdf)