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TPS59641RSLT
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Texas Instruments Power Management - Specialized, VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# TPS59641RSLT++**Texas Instruments** · Power Management - Specialized · VQFN-48(6x6)++TPS59641RSLT from Texas Instruments, in a VQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CTHERM | bidirectional | Thermal sensor connection for the CPU converter; resistor connected to VREF forms a divider with NTC thermistor connected to GND. |+| 2 | COCP-I | input | Resistor to GND (RCOCP) selects 1 of 8 OCP levels of the CPU converter; voltage divider to CIMON. |+| 3 | CIMON | output | Analog current monitor output for the CPU converter; connect 220-nF capacitor to GND for stability. |+| 4 | CCSP1 | input | Positive current sense input for CPU phase 1; connect to most positive node of current sense resistor or inductor DCR sense network. |+| 5 | CCSN1 | input | Negative current sense input for CPU phase 1; connect to most negative node of current sense resistor or inductor DCR sense network; has secondary OVP comparator. |+| 6 | CCSN2 | input | Negative current sense input for CPU phase 2; connect to most negative node of current sense resistor or inductor DCR sense network. |+| 7 | CCSP2 | input | Positive current sense input for CPU phase 2; connect to most positive node of current sense resistor or inductor DCR sense network. |+| 8 | CCSP3 | input | Positive current sense input for CPU phase 3; tie to V3R3 to disable the phase; tie CCSP1 to V3R3 to run GPU converter only. |+| 9 | CCSN3 | input | Negative current sense input for CPU phase 3; part of three-phase current sensing network. |+| 10 | CCOMP | output | Output of GM error amplifier for the CPU converter; resistor to VREF sets the droop gain. |+| 11 | CVFB | input | Voltage sense line tied directly to VCORE of the CPU converter; soft-stop transistor is on this pin; tie to VCORE with 10-Ω resistor to close feedback when µP not in socket. |+| 12 | CGFB | input | Voltage sense return tied for the CPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor is not in the socket. |+| 13 | CF-IMAX | input | Voltage divider to VREF; resistor to GND sets operating frequency of CPU converter; voltage level sets maximum operating current as VIMAX = VREF × IMAX / 255; latched at start-up. |+| 14 | VREF | power_in | 1.7-V, 500-µA reference output; bypass to GND with 0.22-µF ceramic capacitor. |+| 15 | V3R3 | power_in | 3.3-V power input; bypass to GND with ≥1 µF ceramic capacitor. |+| 16 | VR_ON | input | IMVP-7 VR enable; 1V I/O logic level; 100-ns de-bounce; regulator enters controlled soft-stop when brought low. |+| 17 | CPGOOD | tri_state | IMVP-7_PWRGD output for CPU converter; open-drain; upper threshold VDAC +220 mV, lower threshold VDAC -315 mV. |+| 18 | VCLK | input | SVID clock input; 1-V logic level. |+| 19 | ALERT | tri_state | SVID interrupt line, open drain; route between VCLK and VDIO to prevent cross-talk. |+| 20 | VDIO | bidirectional | SVID digital I/O line; 1-V logic level. |+| 21 | VR_HOT | tri_state | IMVP-7 thermal flag open drain output - active low; typically pulled up to 1-V logic level through 56 Ω; fall time < 100 ns; 1-ms de-glitch. |+| 22 | SLEWA | input | Voltage at start-up sets 1 of 7 slew rates for both converters; slow rate is SLEWRATE/4; soft-start and soft-stop rates are SLEWRATE/8; latched at start-up; tie to GND to disable SCLK timer. |+| 23 | GPGOOD | tri_state | IMVP-7_PWRGD output for the GPU converter; open-drain. |+| 24 | GF-IMAX | input | Voltage divider to VREF; resistor to GND sets operating frequency of GPU converter; voltage level sets maximum operating current as VIMAX = VREF × IMAX / 255; latched at start-up. |+| 25 | GGFB | input | Voltage sense return tied for the GPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor is not in the socket. |+| 26 | GVFB | input | Voltage sense line tied directly to VGFX of the GPU converter; soft-stop transistor is on this pin; tie to VGFX with 10-Ω resistor to close feedback. |+| 27 | GCOMP | output | Output of gM error amplifier for the GPU converter; resistor to VREF sets the droop gain. |+| 28 | GCSN | input | Negative current sense input for GPU converter; connect to most negative node of current sense resistor or inductor DCR sense network; has secondary OVP comparator and soft-stop pull-down transistor. |+| 29 | GCSP | input | Positive current sense input for GPU converter; connect to most positive node of current sense resistor or inductor DCR sense network; tie to V3R3 to disable GPU converter. |+| 30 | GIMON | output | Analog current monitor output for the GPU converter; connect 220-nF capacitor to GND for stability. |+| 31 | GOCP-I | input | Voltage divider to GIMON; resistor ratio sets IMON gain; resistor to GND (RGOCP) selects 1 of 8 OCP levels for GPU converter. |+| 32 | GTHERM | bidirectional | Thermal sensor input for GPU converter; resistor connected to VREF forms a divider with NTC thermistor connected to GND. |+| 33 | GSKIP | output | Skip mode control of external driver for GPU converter; 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects 1 of 8 OSR/USR levels. |+| 34 | GPWM | output | PWM control for external driver; 5-V logic level. |+| 35 | CSKIP | output | Skip mode control of external driver for CPU converter; logic HI = FCCM, LO = SKIP; resistor to GND selects 1 of 8 OSR/USR levels; 0.1 V < VCSKIP < 0.3 V at start-up turns OSR off. |+| 36 | CPWM3 | output | PWM control for external driver CPU phase 3; 5V logic level. |+| 37 | VBAT | power_in | Provides VBAT information to on-time circuits for both converters; 10-kΩ series resistor protects adjacent pins from inadvertent shorts due to solder bridges or mis-probing. |+| 38 | CDH2 | output | Top N-channel FET gate drive output for CPU phase 2. |+| 39 | CBST2 | input | Top N-channel FET bootstrap voltage input for CPU phase 2. |+| 40 | CSW2 | bidirectional | Top N-channel FET gate drive return for CPU phase 2; connects to switched node and bootstrap network. |+| 41 | CDL2 | output | Synchronous N-channel FET gate drive output for CPU phase 2. |+| 42 | PGND | power_in | Synchronous N-channel FET gate drive return; gate driver ground; connect directly to gate driver decoupling capacitor ground terminal. |+| 43 | V5DRV | power_in | Power input for gate drivers; connected with external resistor to V5F; decouple with ≥2.2 µF ceramic capacitor. |+| 44 | CDL1 | output | Synchronous N-channel FET gate drive output for CPU phase 1. |+| 45 | CSW1 | bidirectional | Top N-channel FET gate drive return for CPU phase 1; connects to switched node and bootstrap network. |+| 46 | CBST1 | input | Top N-channel FET bootstrap voltage input for CPU phase 1. |+| 47 | CDH1 | output | Top N-channel FET gate drive output for CPU phase 1. |+| 48 | V5 | power_in | 5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic capacitor. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48(6x6) |+| Category | Power Management (PMIC) |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `TPS59641RSLT`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.4x4.4mm`+- 3D model: VQFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps59641rslt-etched.step` / `tps59641rslt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps59641rslt.step` / `tps59641rslt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps51640a) (53 pp, sha256 `1e89e7957ab9138c`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps59641rslt-datasheet.pdf)
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resistor connected to VREF forms a divider with NTC thermistor connected to GND."+ },+ {+ "number": "2",+ "name": "COCP-I",+ "type": "input",+ "description": "Resistor to GND (RCOCP) selects 1 of 8 OCP levels of the CPU converter; voltage divider to CIMON."+ },+ {+ "number": "3",+ "name": "CIMON",+ "type": "output",+ "description": "Analog current monitor output for the CPU converter; connect 220-nF capacitor to GND for stability."+ },+ {+ "number": "4",+ "name": "CCSP1",+ "type": "input",+ "description": "Positive current sense input for CPU phase 1; connect to most positive node of current sense resistor or inductor DCR sense network."+ },+ {+ "number": "5",+ "name": "CCSN1",+ "type": "input",+ "description": "Negative current sense input for CPU phase 1; connect to most negative node of current sense resistor or inductor DCR sense network; has secondary OVP comparator."+ },+ {+ "number": "6",+ "name": "CCSN2",+ "type": "input",+ "description": "Negative current sense input for CPU phase 2; connect to most negative node of current sense resistor or inductor DCR sense network."+ },+ {+ "number": "7",+ "name": "CCSP2",+ "type": "input",+ "description": "Positive current sense input for CPU phase 2; connect to most positive node of current sense resistor or inductor DCR sense network."+ },+ {+ "number": "8",+ "name": "CCSP3",+ "type": "input",+ "description": "Positive current sense input for CPU phase 3; tie to V3R3 to disable the phase; tie CCSP1 to V3R3 to run GPU converter only."+ },+ {+ "number": "9",+ "name": "CCSN3",+ "type": "input",+ "description": "Negative current sense input for CPU phase 3; part of three-phase current sensing network."+ },+ {+ "number": "10",+ "name": "CCOMP",+ "type": "output",+ "description": "Output of GM error amplifier for the CPU converter; resistor to VREF sets the droop gain."+ },+ {+ "number": "11",+ "name": "CVFB",+ "type": "input",+ "description": "Voltage sense line tied directly to VCORE of the CPU converter; soft-stop transistor is on this pin; tie to VCORE with 10-Ω resistor to close feedback when µP not in socket."+ },+ {+ "number": "12",+ "name": "CGFB",+ "type": "input",+ "description": "Voltage sense return tied for the CPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor is not in the socket."+ },+ {+ "number": "13",+ "name": "CF-IMAX",+ "type": "input",+ "description": "Voltage divider to VREF; resistor to GND sets operating frequency of CPU converter; voltage level sets maximum operating current as VIMAX = VREF × IMAX / 255; latched at start-up."+ },+ {+ "number": "14",+ "name": "VREF",+ "type": "power_in",+ "description": "1.7-V, 500-µA reference output; bypass to GND with 0.22-µF ceramic capacitor."+ },+ {+ "number": "15",+ "name": "V3R3",+ "type": "power_in",+ "description": "3.3-V power input; bypass to GND with ≥1 µF ceramic capacitor."+ },+ {+ "number": "16",+ "name": "VR_ON",+ "type": "input",+ "description": "IMVP-7 VR enable; 1V I/O logic level; 100-ns de-bounce; regulator enters controlled soft-stop when brought low."+ },+ {+ "number": "17",+ "name": "CPGOOD",+ "type": "tri_state",+ "description": "IMVP-7_PWRGD output for CPU converter; open-drain; upper threshold VDAC +220 mV, lower threshold VDAC -315 mV."+ },+ {+ "number": "18",+ "name": "VCLK",+ "type": "input",+ "description": "SVID clock input; 1-V logic level."+ },+ {+ "number": "19",+ "name": "ALERT",+ "type": "tri_state",+ "description": "SVID interrupt line, open drain; route between VCLK and VDIO to prevent cross-talk."+ },+ {+ "number": "20",+ "name": "VDIO",+ "type": "bidirectional",+ "description": "SVID digital I/O line; 1-V logic level."+ },+ {+ "number": "21",+ "name": "VR_HOT",+ "type": "tri_state",+ "description": "IMVP-7 thermal flag open drain output - active low; typically pulled up to 1-V logic level through 56 Ω; fall time < 100 ns; 1-ms de-glitch."+ },+ {+ "number": "22",+ "name": "SLEWA",+ "type": "input",+ "description": "Voltage at start-up sets 1 of 7 slew rates for both converters; slow rate is SLEWRATE/4; soft-start and soft-stop rates are SLEWRATE/8; latched at start-up; tie to GND to disable SCLK timer."+ },+ {+ "number": "23",+ "name": "GPGOOD",+ "type": "tri_state",+ "description": "IMVP-7_PWRGD output for the GPU converter; open-drain."+ },+ {+ "number": "24",+ "name": "GF-IMAX",+ "type": "input",+ "description": "Voltage divider to VREF; resistor to GND sets operating frequency of GPU converter; voltage level sets maximum operating current as VIMAX = VREF × IMAX / 255; latched at start-up."+ },+ {+ "number": "25",+ "name": "GGFB",+ "type": "input",+ "description": "Voltage sense return tied for the GPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor is not in the socket."+ },+ {+ "number": "26",+ "name": "GVFB",+ "type": "input",+ "description": "Voltage sense line tied directly to VGFX of the GPU converter; soft-stop transistor is on this pin; tie to VGFX with 10-Ω resistor to close feedback."+ },+ {+ "number": "27",+ "name": "GCOMP",+ "type": "output",+ "description": "Output of gM error amplifier for the GPU converter; resistor to VREF sets the droop gain."+ },+ {+ "number": "28",+ "name": "GCSN",+ "type": "input",+ "description": "Negative current sense input for GPU converter; connect to most negative node of current sense resistor or inductor DCR sense network; has secondary OVP comparator and soft-stop pull-down transistor."+ },+ {+ "number": "29",+ "name": "GCSP",+ "type": "input",+ "description": "Positive current sense input for GPU converter; connect to most positive node of current sense resistor or inductor DCR sense network; tie to V3R3 to disable GPU converter."+ },+ {+ "number": "30",+ "name": "GIMON",+ "type": "output",+ "description": "Analog current monitor output for the GPU converter; connect 220-nF capacitor to GND for stability."+ },+ {+ "number": "31",+ "name": "GOCP-I",+ "type": "input",+ "description": "Voltage divider to GIMON; resistor ratio sets IMON gain; resistor to GND (RGOCP) selects 1 of 8 OCP levels for GPU converter."+ },+ {+ "number": "32",+ "name": "GTHERM",+ "type": "bidirectional",+ "description": "Thermal sensor input for GPU converter; resistor connected to VREF forms a divider with NTC thermistor connected to GND."+ },+ {+ "number": "33",+ "name": "GSKIP",+ "type": "output",+ "description": "Skip mode control of external driver for GPU converter; 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects 1 of 8 OSR/USR levels."+ },+ {+ "number": "34",+ "name": "GPWM",+ "type": "output",+ "description": "PWM control for external driver; 5-V logic level."+ },+ {+ "number": "35",+ "name": "CSKIP",+ "type": "output",+ "description": "Skip mode control of external driver for CPU converter; logic HI = FCCM, LO = SKIP; resistor to GND selects 1 of 8 OSR/USR levels; 0.1 V < VCSKIP < 0.3 V at start-up turns OSR off."+ },+ {+ "number": "36",+ "name": "CPWM3",+ "type": "output",+ "description": "PWM control for external driver CPU phase 3; 5V logic level."+ },+ {+ "number": "37",+ "name": "VBAT",+ "type": "power_in",+ "description": "Provides VBAT information to on-time circuits for both converters; 10-kΩ series resistor protects adjacent pins from inadvertent shorts due to solder bridges or mis-probing."+ },+ {+ "number": "38",+ "name": "CDH2",+ "type": "output",+ "description": "Top N-channel FET gate drive output for CPU phase 2."+ },+ {+ "number": "39",+ "name": "CBST2",+ "type": "input",+ "description": "Top N-channel FET bootstrap voltage input for CPU phase 2."+ },+ {+ "number": "40",+ "name": "CSW2",+ "type": "bidirectional",+ "description": "Top N-channel FET gate drive return for CPU phase 2; connects to switched node and bootstrap network."+ },+ {+ "number": "41",+ "name": "CDL2",+ "type": "output",+ "description": "Synchronous N-channel FET gate drive output for CPU phase 2."+ },+ {+ "number": "42",+ "name": "PGND",+ "type": "power_in",+ "description": "Synchronous N-channel FET gate drive return; gate driver ground; connect directly to gate driver decoupling capacitor ground terminal."+ },+ {+ "number": "43",+ "name": "V5DRV",+ "type": "power_in",+ "description": "Power input for gate drivers; connected with external resistor to V5F; decouple with ≥2.2 µF ceramic capacitor."+ },+ {+ "number": "44",+ "name": "CDL1",+ "type": "output",+ "description": "Synchronous N-channel FET gate drive output for CPU phase 1."+ },+ {+ "number": "45",+ "name": "CSW1",+ "type": "bidirectional",+ "description": "Top N-channel FET gate drive return for CPU phase 1; connects to switched node and bootstrap network."+ },+ {+ "number": "46",+ "name": "CBST1",+ "type": "input",+ "description": "Top N-channel FET bootstrap voltage input for CPU phase 1."+ },+ {+ "number": "47",+ "name": "CDH1",+ "type": "output",+ "description": "Top N-channel FET gate drive output for CPU phase 1."+ },+ {+ "number": "48",+ "name": "V5",+ "type": "power_in",+ "description": "5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic capacitor."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Thermal pad (PAD) is listed as GND but is not a numbered pin; it is the bottom thermal pad of the 6x"+ ],+ "pages_sent": 53,+ "cost_usd": 1.2743,+ "at": "2026-10-01T18:05:14"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps51640a",+ "pages": 53,+ "sha256": "1e89e7957ab9138c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}