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TPS59641RSLT

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Texas Instruments Power Management - Specialized, VQFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps59641rsltfactory-2.0.0extractor-text
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Contents

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TPS59641RSLT

Texas Instruments · Power Management - Specialized · VQFN-48(6x6)

TPS59641RSLT from Texas Instruments, in a VQFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CTHERM bidirectional Thermal sensor input for CPU converter; resistor divider to VREF with NTC thermistor to GND.
2 COCP-I input Over-current protection level select input for CPU converter via resistor to GND.
3 CIMON output Analog current monitor output for CPU converter; connect 220-nF capacitor to GND for stability.
4 CCSP1 input Positive current sense input for CPU converter phase 1.
5 CCSN1 input Negative current sense input for CPU converter phase 1 with secondary OVP comparator.
6 CCSN2 input Negative current sense input for CPU converter phase 2.
7 CCSP2 input Positive current sense input for CPU converter phase 2.
8 CCSP3 input Positive current sense input for CPU converter phase 3; tie to V3R3 to disable phase.
9 CCSN3 input Negative current sense input for CPU converter phase 3.
10 CCOMP output CPU converter error amplifier output with droop gain set by resistor to VREF.
11 CVFB input CPU converter voltage feedback sense at VCORE with soft-stop transistor.
12 CGFB input CPU converter voltage feedback return; tie to GND with 10-Ω resistor when microprocessor not in socket.
13 CF-IMAX input CPU converter frequency and maximum current configuration via voltage divider to VREF.
14 VREF power_out 1.7-V 500-µA reference output; bypass to GND with 0.22-µF capacitor.
15 V3R3 power_in 3.3-V power supply input; bypass to GND with ≥1-µF ceramic capacitor.
16 VR_ON input IMVP-7 VR enable input with 100-ns debounce; low brings regulator to controlled soft-stop.
17 CPGOOD tri_state CPU converter IMVP-7 power good open-drain output.
18 VCLK input SVID clock input with 1-V logic level.
19 ALERT tri_state SVID interrupt line open-drain output; route between VCLK and VDIO to prevent cross-talk.
20 VDIO bidirectional SVID digital I/O line with 1-V logic level.
21 VR_HOT tri_state Thermal flag open-drain output active-low with <100-ns fall time and 1-ms deglitch.
22 SLEWA input Slew rate configuration input; voltage at start-up sets 1 of 7 rates or disables SCLK timer if tied to GND.
23 GPGOOD tri_state GPU converter IMVP-7 power good open-drain output.
24 GF-IMAX input GPU converter frequency and maximum current configuration via voltage divider to VREF.
25 GGFB input GPU converter voltage feedback return; tie to GND with 10-Ω resistor when microprocessor not in socket.
26 GVFB input GPU converter voltage feedback sense at VGFX with soft-stop transistor.
27 GCOMP output GPU converter error amplifier output with droop gain set by resistor to VREF.
28 GCSN input GPU converter negative current sense input with secondary OVP comparator and soft-stop pull-down transistor.
29 GCSP input GPU converter positive current sense input; tie to V3R3 to disable GPU converter.
30 GIMON output Analog current monitor output for GPU converter; connect 220-nF capacitor to GND for stability.
31 GOCP-I input GPU converter over-current protection configuration input via resistor ratio.
32 GTHERM bidirectional Thermal sensor input for GPU converter; resistor divider to VREF with NTC thermistor to GND.
33 GSKIP output GPU converter skip mode control 5-V logic output; HI=FCCM, LO=SKIP; resistor to GND selects 1 of 8 OSR/USR levels.
34 GPWM output GPU converter PWM control 5-V logic output.
35 CSKIP output CPU converter skip mode control 5-V logic output; HI=FCCM, LO=SKIP; 0.1-V to 0.3-V at start-up disables OSR.
36 CPWM3 output CPU converter phase 3 PWM control 5-V logic output for external driver.
37 VBAT power_in System battery voltage input with 10-kΩ series resistor protection from inadvertent shorts.
38 CDH2 output Top N-channel FET gate drive output for CPU converter phase 2.
39 CBST2 input Bootstrap voltage input for CPU converter phase 2 top N-channel FET.
40 CSW2 bidirectional Top N-channel FET gate drive return for CPU converter phase 2.
41 CDL2 output Synchronous N-channel FET gate drive output for CPU converter phase 2.
42 PGND power_in Gate driver power ground; connect directly to V5DRV decoupling capacitor with multiple vias.
43 V5DRV power_in 5-V gate driver power supply input; decouple with ≥2.2-µF ceramic capacitor.
44 CDL1 output Synchronous N-channel FET gate drive output for CPU converter phase 1.
45 CSW1 bidirectional Top N-channel FET gate drive return for CPU converter phase 1.
46 CBST1 input Bootstrap voltage input for CPU converter phase 1 top N-channel FET.
47 CDH1 output Top N-channel FET gate drive output for CPU converter phase 1.
48 V5 power_in 5-V analog power supply input; bypass to GND with ≥1-µF ceramic capacitor.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48(6x6)
Category Power Management (PMIC)
Pins 49

CAD (KiCad official)

  • Symbol: TPS59641RSLT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps59641rslt-etched.step / tps59641rslt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps59641rslt.step / tps59641rslt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (53 pp, sha256 1e89e7957ab9138c, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF