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TPS59641RSLR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# TPS59641RSLR++**Texas Instruments** · DC-DC Converters · VQFN-48-EP(6x6)++TPS59641RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CTHERM | bidirectional | Thermal sensor connection for CPU converter; resistor to VREF forms divider with NTC thermistor to GND. |+| 2 | COCP-I | input | Resistor to GND selects one of eight OCP levels for CPU channel; voltage divider to CIMON sets IMON gain. |+| 3 | CIMON | output | Analog current monitor output for CPU converter with voltage proportional to output current; connect 220-nF capacitor to GND for stability. |+| 4 | CCSP1 | input | Positive current sense input for CPU phase 1; connect to most positive node of current sense network or tie to V3R3 to disable phase. |+| 5 | CCSN1 | input | Negative current sense input for CPU phase 1 with secondary OVP comparator; connect to most negative node of current sense network. |+| 6 | CCSN2 | input | Negative current sense input for CPU phase 2; connect to most negative node of current sense resistor or inductor DCR sense network. |+| 7 | CCSP2 | input | Positive current sense input for CPU phase 2; connect to most positive node of current sense network or tie to V3R3 to disable phase. |+| 8 | CCSP3 | input | Positive current sense input for CPU phase 3; tie to V3R3 to disable the phase for 2-phase operation. |+| 9 | CCSN3 | input | Negative current sense input for CPU phase 3; tie to GND to disable phase for 2-phase operation. |+| 10 | CCOMP | output | Output of gM error amplifier for CPU converter; resistor to VREF sets droop gain for load-line compensation. |+| 11 | CVFB | input | Voltage sense line tied directly to VCORE of CPU converter with soft-stop transistor; tie to VCORE with 10-Ω resistor when microprocessor not in socket. |+| 12 | CGFB | input | Voltage sense return tied for CPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor not in socket. |+| 13 | CF-IMAX | input | Voltage divider to VREF for CPU converter; resistor to GND sets operating frequency and voltage level sets maximum operating current as 8-bit A/D value. |+| 14 | VREF | power_out | 1.7-V, 500-µA reference output for analog circuits; bypass to GND with 0.22-µF ceramic capacitor. |+| 15 | V3R3 | power_in | 3.3-V power input for logic and reference circuits; bypass to GND with ≥1 µF ceramic capacitor. |+| 16 | VR_ON | input | IMVP-7 VR enable input with 1-V logic level and 100-ns de-bounce; regulator enters controlled soft-stop when brought low. |+| 17 | CPGOOD | output | IMVP-7 power good output for CPU converter with open-drain configuration; active when output voltage within ±315 mV of DAC setting. |+| 18 | VCLK | input | SVID bus clock input with 1-V logic level for serial VID communication. |+| 19 | ALERT | output | SVID interrupt line with open-drain configuration; route between VCLK and VDIO to prevent cross-talk. |+| 20 | VDIO | bidirectional | SVID digital I/O line with 1-V logic level for serial communication data. |+| 21 | VR_HOT | output | IMVP-7 thermal flag open-drain output active low; typically pulled up to 1-V through 56-Ω resistor with fall time < 100 ns. |+| 22 | SLEWA | input | Voltage input setting one of seven slew rates for both converters at start-up, latched at startup; tie to GND to disable SCLK timer. |+| 23 | GPGOOD | output | IMVP-7 power good output for GPU converter with open-drain configuration; active when output voltage within ±315 mV of DAC setting. |+| 24 | GF-IMAX | input | Voltage divider to VREF for GPU converter; resistor to GND sets operating frequency and voltage level sets maximum operating current as 8-bit A/D value. |+| 25 | GGFB | input | Voltage sense return tied for GPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor not in socket. |+| 26 | GVFB | input | Voltage sense line tied directly to VGFX of GPU converter with soft-stop transistor; tie to VGFX with 10-Ω resistor when microprocessor not in socket. |+| 27 | GCOMP | output | Output of gM error amplifier for GPU converter; resistor to VREF sets droop gain for load-line compensation. |+| 28 | GCSN | input | Negative current sense input for GPU converter with secondary OVP comparator; includes soft-stop pull-down transistor. |+| 29 | GCSP | input | Positive current sense input for GPU converter; connect to most positive node of current sense network or tie to V3R3 to disable GPU converter. |+| 30 | GIMON | output | Analog current monitor output for GPU converter with voltage proportional to output current; connect 220-nF capacitor to GND for stability. |+| 31 | GOCP-I | input | Voltage divider to GIMON for GPU converter; resistor to GND selects one of eight OCP levels and resistor ratio sets IMON gain. |+| 32 | GTHERM | bidirectional | Thermal sensor input for GPU converter; resistor to VREF forms divider with NTC thermistor to GND for temperature monitoring. |+| 33 | GSKIP | output | Skip mode control output for GPU converter with 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects OSR/USR level. |+| 34 | GPWM | output | PWM control output for external GPU driver with 5-V logic level. |+| 35 | CSKIP | output | Skip mode control output for CPU converter with 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects OSR/USR level. |+| 36 | CPWM3 | output | PWM control output for external CPU phase 3 driver with 5-V logic level. |+| 37 | VBAT | power_in | Input voltage sense for on-time circuits of both converters; 10-kΩ series resistor protects adjacent pins from inadvertent shorts. |+| 38 | CDH2 | output | Top N-channel FET gate drive output for CPU phase 2 with 2.2 A typical source/sink current capability. |+| 39 | CBST2 | input | Bootstrap voltage input for CPU phase 2; typically between 4-5 V above CSW2 for gate drive supply. |+| 40 | CSW2 | bidirectional | Top N-channel FET gate drive return for CPU phase 2; switch node voltage reference for bootstrap circuit. |+| 41 | CDL2 | output | Synchronous N-channel FET gate drive output for CPU phase 2 with 6 A typical sink current capability. |+| 42 | PGND | power_in | Synchronous N-channel FET gate drive return; must connect directly to gate driver decoupling capacitor ground terminal. |+| 43 | V5DRV | power_in | Power input for gate drivers; connect through external resistor to 5V and decouple with ≥2.2 µF ceramic capacitor. |+| 44 | CDL1 | output | Synchronous N-channel FET gate drive output for CPU phase 1 with 6 A typical sink current capability. |+| 45 | CSW1 | bidirectional | Top N-channel FET gate drive return for CPU phase 1; switch node voltage reference for bootstrap circuit. |+| 46 | CBST1 | input | Bootstrap voltage input for CPU phase 1; typically between 4-5 V above CSW1 for gate drive supply. |+| 47 | CDH1 | output | Top N-channel FET gate drive output for CPU phase 1 with 2.2 A typical source/sink current capability. |+| 48 | V5 | power_in | 5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic capacitor. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(6x6) |+| Category | Power Management (PMIC) |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `TPS59641RSLR`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm`+- 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps59641rslr-etched.step` / `tps59641rslr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps59641rslr.step` / `tps59641rslr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps51640a) (53 pp, sha256 `1e89e7957ab9138c`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps59641rslr-datasheet.pdf)
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resistor to VREF forms divider with NTC thermistor to GND."+ },+ {+ "number": "2",+ "name": "COCP-I",+ "type": "input",+ "description": "Resistor to GND selects one of eight OCP levels for CPU channel; voltage divider to CIMON sets IMON gain."+ },+ {+ "number": "3",+ "name": "CIMON",+ "type": "output",+ "description": "Analog current monitor output for CPU converter with voltage proportional to output current; connect 220-nF capacitor to GND for stability."+ },+ {+ "number": "4",+ "name": "CCSP1",+ "type": "input",+ "description": "Positive current sense input for CPU phase 1; connect to most positive node of current sense network or tie to V3R3 to disable phase."+ },+ {+ "number": "5",+ "name": "CCSN1",+ "type": "input",+ "description": "Negative current sense input for CPU phase 1 with secondary OVP comparator; connect to most negative node of current sense network."+ },+ {+ "number": "6",+ "name": "CCSN2",+ "type": "input",+ "description": "Negative current sense input for CPU phase 2; connect to most negative node of current sense resistor or inductor DCR sense network."+ },+ {+ "number": "7",+ "name": "CCSP2",+ "type": "input",+ "description": "Positive current sense input for CPU phase 2; connect to most positive node of current sense network or tie to V3R3 to disable phase."+ },+ {+ "number": "8",+ "name": "CCSP3",+ "type": "input",+ "description": "Positive current sense input for CPU phase 3; tie to V3R3 to disable the phase for 2-phase operation."+ },+ {+ "number": "9",+ "name": "CCSN3",+ "type": "input",+ "description": "Negative current sense input for CPU phase 3; tie to GND to disable phase for 2-phase operation."+ },+ {+ "number": "10",+ "name": "CCOMP",+ "type": "output",+ "description": "Output of gM error amplifier for CPU converter; resistor to VREF sets droop gain for load-line compensation."+ },+ {+ "number": "11",+ "name": "CVFB",+ "type": "input",+ "description": "Voltage sense line tied directly to VCORE of CPU converter with soft-stop transistor; tie to VCORE with 10-Ω resistor when microprocessor not in socket."+ },+ {+ "number": "12",+ "name": "CGFB",+ "type": "input",+ "description": "Voltage sense return tied for CPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor not in socket."+ },+ {+ "number": "13",+ "name": "CF-IMAX",+ "type": "input",+ "description": "Voltage divider to VREF for CPU converter; resistor to GND sets operating frequency and voltage level sets maximum operating current as 8-bit A/D value."+ },+ {+ "number": "14",+ "name": "VREF",+ "type": "power_out",+ "description": "1.7-V, 500-µA reference output for analog circuits; bypass to GND with 0.22-µF ceramic capacitor."+ },+ {+ "number": "15",+ "name": "V3R3",+ "type": "power_in",+ "description": "3.3-V power input for logic and reference circuits; bypass to GND with ≥1 µF ceramic capacitor."+ },+ {+ "number": "16",+ "name": "VR_ON",+ "type": "input",+ "description": "IMVP-7 VR enable input with 1-V logic level and 100-ns de-bounce; regulator enters controlled soft-stop when brought low."+ },+ {+ "number": "17",+ "name": "CPGOOD",+ "type": "output",+ "description": "IMVP-7 power good output for CPU converter with open-drain configuration; active when output voltage within ±315 mV of DAC setting."+ },+ {+ "number": "18",+ "name": "VCLK",+ "type": "input",+ "description": "SVID bus clock input with 1-V logic level for serial VID communication."+ },+ {+ "number": "19",+ "name": "ALERT",+ "type": "output",+ "description": "SVID interrupt line with open-drain configuration; route between VCLK and VDIO to prevent cross-talk."+ },+ {+ "number": "20",+ "name": "VDIO",+ "type": "bidirectional",+ "description": "SVID digital I/O line with 1-V logic level for serial communication data."+ },+ {+ "number": "21",+ "name": "VR_HOT",+ "type": "output",+ "description": "IMVP-7 thermal flag open-drain output active low; typically pulled up to 1-V through 56-Ω resistor with fall time < 100 ns."+ },+ {+ "number": "22",+ "name": "SLEWA",+ "type": "input",+ "description": "Voltage input setting one of seven slew rates for both converters at start-up, latched at startup; tie to GND to disable SCLK timer."+ },+ {+ "number": "23",+ "name": "GPGOOD",+ "type": "output",+ "description": "IMVP-7 power good output for GPU converter with open-drain configuration; active when output voltage within ±315 mV of DAC setting."+ },+ {+ "number": "24",+ "name": "GF-IMAX",+ "type": "input",+ "description": "Voltage divider to VREF for GPU converter; resistor to GND sets operating frequency and voltage level sets maximum operating current as 8-bit A/D value."+ },+ {+ "number": "25",+ "name": "GGFB",+ "type": "input",+ "description": "Voltage sense return tied for GPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor not in socket."+ },+ {+ "number": "26",+ "name": "GVFB",+ "type": "input",+ "description": "Voltage sense line tied directly to VGFX of GPU converter with soft-stop transistor; tie to VGFX with 10-Ω resistor when microprocessor not in socket."+ },+ {+ "number": "27",+ "name": "GCOMP",+ "type": "output",+ "description": "Output of gM error amplifier for GPU converter; resistor to VREF sets droop gain for load-line compensation."+ },+ {+ "number": "28",+ "name": "GCSN",+ "type": "input",+ "description": "Negative current sense input for GPU converter with secondary OVP comparator; includes soft-stop pull-down transistor."+ },+ {+ "number": "29",+ "name": "GCSP",+ "type": "input",+ "description": "Positive current sense input for GPU converter; connect to most positive node of current sense network or tie to V3R3 to disable GPU converter."+ },+ {+ "number": "30",+ "name": "GIMON",+ "type": "output",+ "description": "Analog current monitor output for GPU converter with voltage proportional to output current; connect 220-nF capacitor to GND for stability."+ },+ {+ "number": "31",+ "name": "GOCP-I",+ "type": "input",+ "description": "Voltage divider to GIMON for GPU converter; resistor to GND selects one of eight OCP levels and resistor ratio sets IMON gain."+ },+ {+ "number": "32",+ "name": "GTHERM",+ "type": "bidirectional",+ "description": "Thermal sensor input for GPU converter; resistor to VREF forms divider with NTC thermistor to GND for temperature monitoring."+ },+ {+ "number": "33",+ "name": "GSKIP",+ "type": "output",+ "description": "Skip mode control output for GPU converter with 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects OSR/USR level."+ },+ {+ "number": "34",+ "name": "GPWM",+ "type": "output",+ "description": "PWM control output for external GPU driver with 5-V logic level."+ },+ {+ "number": "35",+ "name": "CSKIP",+ "type": "output",+ "description": "Skip mode control output for CPU converter with 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects OSR/USR level."+ },+ {+ "number": "36",+ "name": "CPWM3",+ "type": "output",+ "description": "PWM control output for external CPU phase 3 driver with 5-V logic level."+ },+ {+ "number": "37",+ "name": "VBAT",+ "type": "power_in",+ "description": "Input voltage sense for on-time circuits of both converters; 10-kΩ series resistor protects adjacent pins from inadvertent shorts."+ },+ {+ "number": "38",+ "name": "CDH2",+ "type": "output",+ "description": "Top N-channel FET gate drive output for CPU phase 2 with 2.2 A typical source/sink current capability."+ },+ {+ "number": "39",+ "name": "CBST2",+ "type": "input",+ "description": "Bootstrap voltage input for CPU phase 2; typically between 4-5 V above CSW2 for gate drive supply."+ },+ {+ "number": "40",+ "name": "CSW2",+ "type": "bidirectional",+ "description": "Top N-channel FET gate drive return for CPU phase 2; switch node voltage reference for bootstrap circuit."+ },+ {+ "number": "41",+ "name": "CDL2",+ "type": "output",+ "description": "Synchronous N-channel FET gate drive output for CPU phase 2 with 6 A typical sink current capability."+ },+ {+ "number": "42",+ "name": "PGND",+ "type": "power_in",+ "description": "Synchronous N-channel FET gate drive return; must connect directly to gate driver decoupling capacitor ground terminal."+ },+ {+ "number": "43",+ "name": "V5DRV",+ "type": "power_in",+ "description": "Power input for gate drivers; connect through external resistor to 5V and decouple with ≥2.2 µF ceramic capacitor."+ },+ {+ "number": "44",+ "name": "CDL1",+ "type": "output",+ "description": "Synchronous N-channel FET gate drive output for CPU phase 1 with 6 A typical sink current capability."+ },+ {+ "number": "45",+ "name": "CSW1",+ "type": "bidirectional",+ "description": "Top N-channel FET gate drive return for CPU phase 1; switch node voltage reference for bootstrap circuit."+ },+ {+ "number": "46",+ "name": "CBST1",+ "type": "input",+ "description": "Bootstrap voltage input for CPU phase 1; typically between 4-5 V above CSW1 for gate drive supply."+ },+ {+ "number": "47",+ "name": "CDH1",+ "type": "output",+ "description": "Top N-channel FET gate drive output for CPU phase 1 with 2.2 A typical source/sink current capability."+ },+ {+ "number": "48",+ "name": "V5",+ "type": "power_in",+ "description": "5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic capacitor."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 53,+ "cost_usd": 0.418,+ "at": "2026-10-01T17:45:56"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps51640a",+ "pages": 53,+ "sha256": "1e89e7957ab9138c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}