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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS59641RSLR

Texas Instruments · DC-DC Converters · VQFN-48-EP(6x6)

TPS59641RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CTHERM	bidirectional	Thermal sensor connection for CPU converter; resistor to VREF forms divider with NTC thermistor to GND.
2	COCP-I	input	Resistor to GND selects one of eight OCP levels for CPU channel; voltage divider to CIMON sets IMON gain.
3	CIMON	output	Analog current monitor output for CPU converter with voltage proportional to output current; connect 220-nF capacitor to GND for stability.
4	CCSP1	input	Positive current sense input for CPU phase 1; connect to most positive node of current sense network or tie to V3R3 to disable phase.
5	CCSN1	input	Negative current sense input for CPU phase 1 with secondary OVP comparator; connect to most negative node of current sense network.
6	CCSN2	input	Negative current sense input for CPU phase 2; connect to most negative node of current sense resistor or inductor DCR sense network.
7	CCSP2	input	Positive current sense input for CPU phase 2; connect to most positive node of current sense network or tie to V3R3 to disable phase.
8	CCSP3	input	Positive current sense input for CPU phase 3; tie to V3R3 to disable the phase for 2-phase operation.
9	CCSN3	input	Negative current sense input for CPU phase 3; tie to GND to disable phase for 2-phase operation.
10	CCOMP	output	Output of gM error amplifier for CPU converter; resistor to VREF sets droop gain for load-line compensation.
11	CVFB	input	Voltage sense line tied directly to VCORE of CPU converter with soft-stop transistor; tie to VCORE with 10-Ω resistor when microprocessor not in socket.
12	CGFB	input	Voltage sense return tied for CPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor not in socket.
13	CF-IMAX	input	Voltage divider to VREF for CPU converter; resistor to GND sets operating frequency and voltage level sets maximum operating current as 8-bit A/D value.
14	VREF	power_out	1.7-V, 500-µA reference output for analog circuits; bypass to GND with 0.22-µF ceramic capacitor.
15	V3R3	power_in	3.3-V power input for logic and reference circuits; bypass to GND with ≥1 µF ceramic capacitor.
16	VR_ON	input	IMVP-7 VR enable input with 1-V logic level and 100-ns de-bounce; regulator enters controlled soft-stop when brought low.
17	CPGOOD	output	IMVP-7 power good output for CPU converter with open-drain configuration; active when output voltage within ±315 mV of DAC setting.
18	VCLK	input	SVID bus clock input with 1-V logic level for serial VID communication.
19	ALERT	output	SVID interrupt line with open-drain configuration; route between VCLK and VDIO to prevent cross-talk.
20	VDIO	bidirectional	SVID digital I/O line with 1-V logic level for serial communication data.
21	VR_HOT	output	IMVP-7 thermal flag open-drain output active low; typically pulled up to 1-V through 56-Ω resistor with fall time < 100 ns.
22	SLEWA	input	Voltage input setting one of seven slew rates for both converters at start-up, latched at startup; tie to GND to disable SCLK timer.
23	GPGOOD	output	IMVP-7 power good output for GPU converter with open-drain configuration; active when output voltage within ±315 mV of DAC setting.
24	GF-IMAX	input	Voltage divider to VREF for GPU converter; resistor to GND sets operating frequency and voltage level sets maximum operating current as 8-bit A/D value.
25	GGFB	input	Voltage sense return tied for GPU converter; tie to GND with 10-Ω resistor to close feedback when microprocessor not in socket.
26	GVFB	input	Voltage sense line tied directly to VGFX of GPU converter with soft-stop transistor; tie to VGFX with 10-Ω resistor when microprocessor not in socket.
27	GCOMP	output	Output of gM error amplifier for GPU converter; resistor to VREF sets droop gain for load-line compensation.
28	GCSN	input	Negative current sense input for GPU converter with secondary OVP comparator; includes soft-stop pull-down transistor.
29	GCSP	input	Positive current sense input for GPU converter; connect to most positive node of current sense network or tie to V3R3 to disable GPU converter.
30	GIMON	output	Analog current monitor output for GPU converter with voltage proportional to output current; connect 220-nF capacitor to GND for stability.
31	GOCP-I	input	Voltage divider to GIMON for GPU converter; resistor to GND selects one of eight OCP levels and resistor ratio sets IMON gain.
32	GTHERM	bidirectional	Thermal sensor input for GPU converter; resistor to VREF forms divider with NTC thermistor to GND for temperature monitoring.
33	GSKIP	output	Skip mode control output for GPU converter with 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects OSR/USR level.
34	GPWM	output	PWM control output for external GPU driver with 5-V logic level.
35	CSKIP	output	Skip mode control output for CPU converter with 5-V logic level; logic HI = FCCM, LO = SKIP; resistor to GND selects OSR/USR level.
36	CPWM3	output	PWM control output for external CPU phase 3 driver with 5-V logic level.
37	VBAT	power_in	Input voltage sense for on-time circuits of both converters; 10-kΩ series resistor protects adjacent pins from inadvertent shorts.
38	CDH2	output	Top N-channel FET gate drive output for CPU phase 2 with 2.2 A typical source/sink current capability.
39	CBST2	input	Bootstrap voltage input for CPU phase 2; typically between 4-5 V above CSW2 for gate drive supply.
40	CSW2	bidirectional	Top N-channel FET gate drive return for CPU phase 2; switch node voltage reference for bootstrap circuit.
41	CDL2	output	Synchronous N-channel FET gate drive output for CPU phase 2 with 6 A typical sink current capability.
42	PGND	power_in	Synchronous N-channel FET gate drive return; must connect directly to gate driver decoupling capacitor ground terminal.
43	V5DRV	power_in	Power input for gate drivers; connect through external resistor to 5V and decouple with ≥2.2 µF ceramic capacitor.
44	CDL1	output	Synchronous N-channel FET gate drive output for CPU phase 1 with 6 A typical sink current capability.
45	CSW1	bidirectional	Top N-channel FET gate drive return for CPU phase 1; switch node voltage reference for bootstrap circuit.
46	CBST1	input	Bootstrap voltage input for CPU phase 1; typically between 4-5 V above CSW1 for gate drive supply.
47	CDH1	output	Top N-channel FET gate drive output for CPU phase 1 with 2.2 A typical source/sink current capability.
48	V5	power_in	5-V power input for analog circuits; connect through resistor to 5-V plane and bypass to GND with ≥1 µF ceramic capacitor.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-48-EP(6x6)
Category	Power Management (PMIC)
Pins	49

CAD (KiCad official)

Symbol: TPS59641RSLR
Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: tps59641rslr-etched.step / tps59641rslr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps59641rslr.step / tps59641rslr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (53 pp, sha256 1e89e7957ab9138c, retrieved 2026-10-01, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF