# TPS59632QRHBRQ1

**Texas Instruments** · AC-DC Controllers And Regulators · QFN-32(5x5)

TPS59632QRHBRQ1 from Texas Instruments, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA | bidirectional | I2C digital data line, with recommended input voltage limited to -0.1 V to 3.5 V. |
| 2 | VDD | power_in | 3.3-V digital power input that must be bypassed to GND with at least 1 µF; supply range is 3.1 V to 3.5 V. |
| 3 | PGOOD | output | Open-drain power good output that can be configured to go low when the current reaches 70% of the OCP setting value. |
| 4 | PWM3 | output | PWM control for the external driver at 5-V logic level; the controller forces the 3-state level when needed. |
| 5 | PWM2 | output | PWM control for the external driver at 5-V logic level; the controller forces the 3-state level when needed. |
| 6 | PWM1 | output | PWM control for the external driver at 5-V logic level; the controller forces the 3-state level when needed. |
| 7 | SKIP | output | Active high sets forced continuous conduction mode and active low sets skip mode for the synchronous buck MOSFETs; it must connect to the matching driver pin. |
| 8 | EN | input | Enable input with 100-ns de-bounce; when low the regulator enters low-power mode and retains start-up settings. |
| 9 | O-USR | input | Voltage divider to VREG; a resistor to GND selects the pulse-truncation and OSR level, and the voltage at this pin selects the USR level. |
| 10 | FREQ-P | input | A resistor to GND sets the per-phase switching frequency and a resistor to VREF must keep the pin voltage above 0.8 V. |
| 11 | RAMP | input | Voltage divider to VREF; a resistor to GND sets the ramp setting voltage and can override the factory ramp setting. |
| 12 | OCP-I | bidirectional | Voltage divider to IMON whose ratio sets the IMON gain; a resistor to GND selects 1 of 8 OCP levels per phase, latched at start-up. |
| 13 | IMON | output | Analog current monitor output following VIMON = Σ VISENSE × (1 + RIMON / ROCP). |
| 14 | VINTF | power_in | Input voltage to power the I2C interface logic, supplied from 1.7 V to 3.5 V; it can be tied to VDD if 3.3-V logic is needed. |
| 15 | SLEWA | input | Voltage sets the 3 LSBs of the I2C address and the resistance to GND selects 1 of 8 slew rates, both latched at start-up. |
| 16 | VBAT | power_in | 10-kΩ resistor to VBAT provides input-voltage information to the on-time circuits; VBAT must not exceed 28 V. |
| 17 | CSP1 | input | Positive current sense input; tie to 3.3 V to disable the phase, with CSP3, CSP2, CSP1 disabled in that order. |
| 18 | CSN1 | input | Negative current sense input that includes a secondary OVP comparator and the soft-stop pulldown transistor. |
| 19 | CSN2 | input | Negative current sense input connected to the most negative node of the current sense resistor or inductor DCR network. |
| 20 | CSP2 | input | Positive current sense input; tie to 3.3 V to disable the phase, with CSP3, CSP2, CSP1 disabled in that order. |
| 21 | CSP3 | input | Positive current sense input; tie to 3.3 V to disable the phase, with CSP3, CSP2, CSP1 disabled in that order. |
| 22 | CSN3 | input | Negative current sense input connected to the most negative node of the current sense resistor or inductor DCR network. |
| 23 | GFB | input | Voltage sense return that ties to GND on the PCB through a 10-Ω resistor when the µP is not populated. |
| 24 | VFB | input | Voltage sense line tied to the VOUT sense point, with resistance between VFB and GFB greater than 1 MΩ. |
| 25 | DROOP | output | Error amplifier output; a resistor pair from VREF to COMP to DROOP sets the droop gain. |
| 26 | COMP | input | Error amplifier summing node; RCOMP from VREF and RDROOP to DROOP set the droop gain. |
| 27 | VREF | power_out | 1.7-V, 500-µA reference that must be bypassed to GND with a 0.22-µF ceramic capacitor. |
| 28 | V5A | power_in | 5-V power input for analog circuits from 4.5 V to 5.5 V, bypassed to GND with at least 1 µF ceramic capacitor. |
| 29 | GND | power_in | Analog circuit reference that must be tied to a quiet point on the ground plane. |
| 30 | NC | unconnected | No connect; leave floating. |
| 31 | SCL | input | I2C digital clock line. |
| 32 | NC | unconnected | No connect; leave floating. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-32(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage V5A | V5A | -0.3 |  | 6 | V |  | 5 |
| Input voltage VDD, O-USR, RAMP, OCP-I, VFB, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3, VINTF, SDA, SCL, FREQ-P, SLEWA, EN, NC | VDD, O-USR, RAMP, OCP-I, VFB, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3, VINTF, SDA, SCL, FREQ-P, SLEWA, EN, NC | -0.3 |  | 3.6 | V |  | 5 |
| Input voltage VBAT | VBAT | -0.3 |  | 30 | V |  | 5 |
| Input voltage COMP | COMP | -0.3 |  | 3.6 | V |  | 5 |
| Input voltage GFB | GFB | -0.2 |  | 0.2 | V |  | 5 |
| Output voltage PGOOD, IMON, VREF, DROOP | PGOOD, IMON, VREF, DROOP | -0.3 |  | 3.6 | V |  | 5 |
| Output voltage PWM3, PWM2, PWM1, SKIP | PWM3, PWM2, PWM1, SKIP | -0.3 |  | 6 | V |  | 5 |
| Junction temperature range | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature | Tstg | -55 |  | 150 | °C |  | 5 |
| Recommended input voltage V5A | V5A | -0.1 |  | 5.5 | V |  | 5 |
| Recommended input voltage VDD, O-USR, RAMP, OCP-I, VFB, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3, VINTF, SDA, SCL, FREQ-P, SLEWA, EN, NC | VDD, O-USR, RAMP, OCP-I, VFB, CSP1, CSP2, CSP3, CSN1, CSN2, CSN3, VINTF, SDA, SCL, FREQ-P, SLEWA, EN, NC | -0.1 |  | 3.5 | V |  | 5 |
| Recommended input voltage VBAT | VBAT | -0.1 |  | 28 | V |  | 5 |
| Recommended input voltage COMP | COMP | -0.1 |  | 3.5 | V |  | 5 |
| Recommended input voltage GFB | GFB | -0.1 |  | 0.1 | V |  | 5 |
| Recommended output voltage PGOOD, IMON, VREF, DROOP | PGOOD, IMON, VREF, DROOP | -0.1 |  | 3.5 | V |  | 5 |
| Recommended output voltage PWM3, PWM2, PWM1, SKIP | PWM3, PWM2, PWM1, SKIP | -0.1 |  | 5.5 | V |  | 5 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 37.2 |  | °C/W |  | 6 |
| Junction-to-case (top) thermal resistance | RθJCtop |  | 31.9 |  | °C/W |  | 6 |
| Junction-to-board thermal resistance | RθJB |  | 8.1 |  | °C/W |  | 6 |
| Junction-to-case (bottom) thermal resistance | RθJCbot |  | 2.2 |  | °C/W |  | 6 |
| V5A supply current, 3-phase | IV5-3P | 3.6 |  | 6 | mA | VVDAC < VVFB < (VVDAC + 100 mV), EN = HI | 6 |
| VDD supply current, 3-phase | IVDD-3P | 0.2 |  | 0.8 | mA | VVDAC < VVFB < (VVDAC + 100 mV), EN = HI; digital buses idle | 6 |
| V5A supply current, 1-phase | IV5-1P | 3.5 |  | 6 | mA | VDAC < VFB < (VVDAC + 100 mV) EN = HI | 6 |
| VDD supply current, 1-phase | IVDD-1P | 0.2 |  | 0.8 | mA | VDAC < VFB < (VVDAC + 100 mV), EN = HI; digital buses idle | 6 |
| V5A standby current | IV5STBY | 125 |  | 200 | µA | EN = LO | 6 |
| VDD standby current | IVDDSTBY | 23 |  | 40 | µA | EN = LO | 6 |
| V5A UVLO OK threshold | VUVLOH | 4.2 | 4.4 | 4.52 | V | VVFB < 200 mV. Ramp up; VVDD > 3 V; EN = HI; Switching begins. | 6 |
| V5A UVLO fault threshold | VUVLOL | 4 | 4.2 | 4.35 | V | Ramp down; EN = HI; VVDD > 3 V; VVFB = 100 mV. Switching stops | 6 |
| VDD UVLO OK threshold | V3UVLOH | 2.5 | 2.8 | 3 | V | VVFB < 200 mV. Ramp up; VV5A > 4.5 V; EN = HI; Switching begins. | 6 |
| VDD UVLO fault threshold | V3UVLOL | 2.4 | 2.6 | 2.8 | V | Ramp down; EN = HI; V5A > 4.5 V; VFB = 100 mV. Switching stops. | 6 |
| VFB tolerance | VDAC1 | -9 |  | 9 | mV | 1.36 V ≤ VVFB ≤ 1.52 V, IOUT = 0 A | 6 |
| VFB tolerance | VDAC2 | -8 |  | 8 | mV | 1.0 V ≤ VVFB ≤ 1.35 V; IOUT = 0 A | 6 |
| VFB tolerance | VDAC3 | -7 |  | 7 | mV | 0.5 V ≤ VVFB ≤ 0.99 V; IOUT = 0 A | 6 |
| VREF output | VVREF | 1.66 | 1.7 | 1.74 | V | 4.5 V ≤ VV5A ≤ 5.5 V, IVREF = 0 A | 6 |
| VREF output source | VVREFSRC | -4 |  | -3 | mV | 0 A ≤ IREF ≤ 500 µA, HP-2 | 6 |
| Current sense pin input bias current | ICS | -500 | 0.2 | 500 | nA | CSPx and CSNx | 7 |
| Internal current sense gain | ACSINT | 5.8 | 6 | 6.2 | V/V | Gain from CSPx, CSNx to PWM comparator, RSKIP = Open | 7 |
| Internal current share tolerance | IBAL_TOL | -3 |  | 3 | % | VDAC = 1.70 V, VCSP1, VCSN1 = VCSP2, VCSN2 = VCSP3, VCSN3 = VOCPP_MIN | 7 |
| OVP fixed voltage | VOVPH | 1.6 | 1.7 | 1.8 | V | VCSN1 > VOVPH for 1 µs | 8 |
| Soft-stop transistor resistance | RSFTSTP | 100 | 200 |  | Ω | Connected to CSN1 | 8 |
| PGOOD high threshold | VPGDH | 185 |  | 245 | mV | Measured at the VFB pin with respect to VID code, device latches OFF | 8 |
| PGOOD low threshold | VPGDL | -348 |  | -280 | mV | Measured at the VFB pin with respect to VID code, device latches OFF | 8 |
| PWMx / SKIP output low voltage | VP-S_L | 0.15 |  | 0.3 | V | ILOAD = ± 1 mA | 8 |
| PWMx / SKIP 3-state voltage | VPW-SKLK | 1.6 | 1.7 | 1.8 | V | ILOAD = ± 100 µA | 8 |
| SDA pulldown resistance | RVRTTL | 4 |  | 15 | Ω | SDA, V = 0.31 V | 8 |
| PGOOD pulldown resistance | RVRPG | 36 |  | 50 | Ω | PGOOD, V = 0.31 V | 8 |
| Logic leakage current | IVRTTLK | -2 | 0.2 | 2 | µA | SDA, SCL = 1.8 V, PGOOD = 3.3 V | 8 |
| I2C low-level input voltage | VIL,I2C |  |  | 0.6 | V | SCL, SDA, VINTF = 1.8 V | 8 |
| I2C high-level input voltage | VIH,I2C | 1.2 |  |  | V | SCL, SDA, VINTF = 1.8 V | 8 |
| I/O leakage, EN | IENH | 24 |  | 40 | µA | VEN = 1.8 V | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 5 | 7 | 9 | mV | ROCP-I = 20 kΩ +/- 1% | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 7 | 10 | 13 | mV | ROCP-I = 24 kΩ +/- 1% | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 10 | 14 | 18 | mV | ROCP-I = 30 kΩ +/- 1% | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 15 | 19 | 23 | mV | ROCP-I = 39 kΩ +/- 1% | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 21 | 25 | 29 | mV | ROCP-I = 56 kΩ +/- 1% | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 28 | 32 | 36 | mV | ROCP-I = 75 kΩ +/- 1% | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 36 | 40 | 44 | mV | ROCP-I = 100 kΩ +/- 1% | 8 |
| OCP voltage (valley current limit at CSPx, CSNx) | VOCP | 45 | 49 | 53 | mV | ROCP-I = 150 kΩ +/- 1% | 8 |

## CAD (KiCad official)

- Symbol: `TPS59632QRHBRQ1`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `tps59632qrhbrq1-etched.step` / `tps59632qrhbrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps59632qrhbrq1.step` / `tps59632qrhbrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps59632-q1.pdf) (53 pp, sha256 `11f0d28d915f2217`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps59632qrhbrq1-datasheet.pdf)