component
TPS57160ZQDGQRQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, MSOP-10-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS57160ZQDGQRQ1
Texas Instruments · DC-DC Converters · MSOP-10-EP
TPS57160ZQDGQRQ1 from Texas Instruments, in a MSOP-10-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | A bootstrap capacitor is required between BOOT and PH; if its voltage is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. |
| 2 | VIN | power_in | Input supply voltage, 3.5 V to 60 V. |
| 3 | EN | input | Enable pin with internal pullup current source; pull below 1.2 V to disable and float to enable, and adjust the input undervoltage lockout with two resistors. |
| 4 | SS/TR | input | Slow-start and tracking pin; an external capacitor connected to this pin sets the output rise time, and its voltage overrides the internal reference so it can be used for tracking and sequencing. |
| 5 | RT/CLK | input | Resistor timing and external clock input; with a resistor to ground an internal amplifier holds a fixed voltage to set the switching frequency, and if pulled above the PLL upper threshold it becomes a high-impedance synchronization input. |
| 6 | PWRGD | output | Open-drain output that asserts low if the output voltage is low due to thermal shutdown, dropout, overvoltage, or shutdown. |
| 7 | VSENSE | input | Inverting node of the transconductance (gm) error amplifier. |
| 8 | COMP | output | Error amplifier output and input to the output switch current comparator; frequency compensation components connect to COMP. |
| 9 | GND | power_in | Ground; must be electrically connected to the exposed thermal pad on the printed circuit board for proper operation. |
| 10 | PH | input | The source of the internal high-side power MOSFET. |
| 11 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-10-EP |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN | VIN | -0.3 | 65 | V | 4 | ||
| Input voltage EN | EN | -0.3 | 5 | V | 4 | ||
| Input voltage BOOT | BOOT | 73 | V | 4 | |||
| Input voltage VSENSE | VSENSE | -0.3 | 3 | V | 4 | ||
| Input voltage COMP | COMP | -0.3 | 3 | V | 4 | ||
| Input voltage PWRGD | PWRGD | -0.3 | 6 | V | 4 | ||
| Input voltage SS/TR | SS/TR | -0.3 | 3 | V | 4 | ||
| Input voltage RT/CLK | RT/CLK | -0.3 | 3.6 | V | 4 | ||
| Voltage BOOT to PH | BOOT-PH | 8 | V | 4 | |||
| Output voltage PH | VOUT | -0.6 | 65 | V | dc | 4 | |
| Output voltage PH | VOUT | -1 | 65 | V | 200 ns | 4 | |
| Output voltage PH | VOUT | -2 | 65 | V | 30 ns | 4 | |
| Sink current PWRGD | ISINK | 10 | mA | PWRGD | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Operating ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance (standard board) | RθJA | 67.4 | °C/W | DGQ, standard board | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 46.7 | °C/W | DGQ | 5 | ||
| Junction-to-board thermal resistance | RθJB | 38.4 | °C/W | DGQ | 5 | ||
| Junction-to-top characterization parameter | ψJT | 1.9 | °C/W | DGQ | 5 | ||
| Junction-to-board characterization parameter | ψJB | 38.1 | °C/W | DGQ | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 15.9 | °C/W | DGQ | 5 | ||
| Operating input voltage | VIN | 3.5 | 60 | V | 5 | ||
| Internal undervoltage lockout threshold | VUVLO | 2.5 | V | No voltage hysteresis, rising and falling | 5 | ||
| Shutdown supply current | IQ(SD) | 1.5 | 4 | μA | EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V | 5 | |
| Shutdown supply current | IQ(SD) | 1.9 | 6.5 | μA | EN = 0 V, 125°C, 3.5 V ≤ VIN ≤ 60 V | 5 | |
| Operating nonswitching supply current | IQ | 116 | 136 | μA | VSENSE = 0.83 V, VIN = 12 V, TJ = 25°C | 5 | |
| Enable threshold voltage | VEN | 1.15 | 1.25 | 1.36 | V | No voltage hysteresis, rising and falling, TJ = 25°C | 5 |
| Enable input current | IEN | -3.8 | μA | Enable threshold +50 mV | 5 | ||
| Enable input current | IEN | -0.9 | μA | Enable threshold -50 mV | 5 | ||
| Hysteresis current | IHYS | -2.9 | μA | 5 | |||
| Voltage reference | VREF | 0.792 | 0.8 | 0.808 | V | 5 | |
| High-side MOSFET on-resistance | RDS(on) | 300 | mΩ | VIN = 3.5 V, BOOT-PH = 3 V | 5 | ||
| High-side MOSFET on-resistance | RDS(on) | 200 | 410 | mΩ | VIN = 12 V, BOOT-PH = 6 V | 5 | |
| Error amplifier input current | IIN(EA) | 50 | nA | 5 | |||
| Error amplifier source/sink | ICOMP | -7 | 7 | μA | V(COMP) = 1 V, 100-mV overdrive | 5 | |
| Error amplifier transconductance (gM) | gM | 97 | μMhos | -2 μA < ICOMP < 2 μA, VCOMP = 1 V | 5 | ||
| Error amplifier transconductance during slow start | gM | 26 | μMhos | -2 μA < ICOMP < 2 μA, VCOMP = 1 V, VVSENSE = 0.4 V | 5 | ||
| Error amplifier dc gain | AVOL | 10000 | V/V | VVSENSE = 0.8 V | 5 | ||
| Error amplifier bandwidth | BW | 2700 | kHz | 5 | |||
| COMP to switch current transconductance | gCOMP | 6 | A/V | 5 | |||
| Current limit threshold | ILIM | 1.8 | 2.7 | A | VIN = 12 V, TJ = 25°C | 6 | |
| Thermal shutdown | TSD | 182 | °C | 6 | |||
| Switching frequency range using RT mode | fSW | 100 | 2500 | kHz | VIN = 12 V | 6 | |
| Switching frequency | fSW | 450 | 581 | 720 | kHz | VIN = 12 V, RT = 200 kΩ | 6 |
| Switching frequency range using CLK mode | fSW | 300 | 2200 | kHz | VIN = 12 V | 6 | |
| Minimum CLK input pulse width | tW(CLK) | 40 | ns | 6 | |||
| RT/CLK high threshold | VRT/CLK(H) | 1.9 | 2.2 | V | VIN = 12 V | 6 | |
| RT/CLK low threshold | VRT/CLK(L) | 0.45 | 0.7 | V | VIN = 12 V | 6 | |
| RT/CLK falling edge to PH rising edge delay | tD | 60 | ns | Measured at 500 kHz with RT resistor in series | 6 | ||
| PLL lock in time | tLOCK | 100 | μs | Measured at 500 kHz | 6 | ||
| SS/TR charge current | ISS/TR | 2 | μA | VSS/TR = 0.4 V | 6 | ||
| SS/TR-to-VSENSE matching | VSS/TR-VSENSE | 45 | mV | VSS/TR = 0.4 V | 6 | ||
| SS/TR-to-reference crossover | VSS/TR | 1 | V | 98% nominal | 6 | ||
| SS/TR discharge current (overload) | ISS/TR(dis) | 112 | μA | VSENSE = 0 V, V(SS/TR) = 0.4 V | 6 | ||
| SS/TR discharge voltage | VSS/TR(dis) | 54 | mV | VSENSE = 0 V | 6 | ||
| PWRGD VSENSE threshold falling (Fault) | VVSENSE | 92 | % | VSENSE falling (Fault) | 6 | ||
| PWRGD VSENSE threshold rising (Good) | VVSENSE | 94 | % | VSENSE rising (Good) | 6 | ||
| PWRGD VSENSE threshold rising (Fault) | VVSENSE | 109 | % | VSENSE rising (Fault) | 6 | ||
| PWRGD VSENSE threshold falling (Good) | VVSENSE | 107 | % | VSENSE falling (Good) | 6 | ||
| PWRGD threshold hysteresis | VHYS | 2 | % | VSENSE falling | 6 | ||
| PWRGD output high leakage | IOH(PWRGD) | 10 | nA | VSENSE = VREF, V(PWRGD) = 5.5 V, TJ = 25°C | 6 | ||
| PWRGD on resistance | RDS(on) | 50 | Ω | I(PWRGD) = 3 mA, VSENSE < 0.79 V | 6 | ||
| Minimum VIN for defined PWRGD output | VIN(min) | 0.95 | 1.5 | V | V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | This feedback-resistor voltage divider network ties the output voltage (VOUT) to the VSENSE pin as a copper | 40 |
CAD (KiCad official)
- Symbol:
TPS57160ZQDGQRQ1 - Footprint:
Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm - 3D model: MSOP-10-EP (KiCad packages3D, STEP)
- 3D model files:
tps57160zqdgqrq1-etched.step/tps57160zqdgqrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps57160zqdgqrq1.step/tps57160zqdgqrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (56 pp, sha256
48ae8e64b0bcf0ee, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).