TPS57114MRTETEP from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Input supply voltage, 2.95 to 6 V.
2	VIN	power_in	Input supply voltage, 2.95 to 6 V.
3	GND	power_in	Power ground; electrically connect directly to the thermal pad under the IC.
4	GND	power_in	Power ground; electrically connect directly to the thermal pad under the IC.
5	AGND	power_in	Analog ground; connect electrically to GND close to the device.
6	VSENSE	input	Inverting node of the transconductance (gm) error amplifier.
7	COMP	output	Error amplifier output and input to the output-switch current comparator; connect frequency-compensation components to this pin.
8	RT/CLK	input	Resistor-timing or external-clock input pin.
9	SS/TR	input	Slow start and tracking; an external capacitor sets the output-voltage rise time, and the pin can also be used for tracking.
10	PH	power_out	Source of the internal high-side power MOSFET and drain of the internal low-side (synchronous) rectifier MOSFET.
11	PH	power_out	Source of the internal high-side power MOSFET and drain of the internal low-side (synchronous) rectifier MOSFET.
12	PH	power_out	Source of the internal high-side power MOSFET and drain of the internal low-side (synchronous) rectifier MOSFET.
13	BOOT	passive	Requires a bootstrap capacitor between BOOT and PH; if its voltage is below the BOOT UVLO minimum the output is forced off until the capacitor recharges.
14	PWRGD	output	Open-drain output that asserts low if output voltage is low due to thermal shutdown, overcurrent, overvoltage, undervoltage, or EN shutdown.
15	EN	input	Enable pin with internal pullup current source; pull below 1.2 V to disable, float to enable, or use two resistors to set the on-off threshold (adjust UVLO).
16	VIN	power_in	Input supply voltage, 2.95 to 6 V.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-16-EP(3x3)
Category	Power Supply Chip
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Quiescent current	Iq		515	750	µA	V(VSENSE) = 0.9 V, V(VIN) = 5 V, RT = 400 kΩ	6
Shutdown supply current			5.5	15	µA	V(EN) = 0 V, 2.95 V ≤ V(VIN) ≤ 6 V	6
Voltage reference		0.79	0.8	0.81	V	2.95 V ≤ V(VIN) ≤ 6 V, -55°C < TJ < 150°C	6
High-side switch resistance			12	30	mΩ	BOOT-PH = 5 V	6
High-side switch resistance			16	30	mΩ	BOOT-PH = 2.95 V	6
Low-side switch resistance			13	30	mΩ	V(VIN) = 5 V	6
Low-side switch resistance			17	30	mΩ	V(VIN) = 2.95 V	6
Error-amplifier source and sink current		-20		20	µA	V(COMP) = 1 V, 100-mV overdrive	6
Current-limit threshold		5		6.4	A	V(VIN) = 2.95 V, 25°C < TJ < 150°C	7
Current-limit threshold		4			A	TJ = -55°C	7
Current-limit threshold		4.4		5.56	A	V(VIN) = 6 V, 25°C < TJ < 150°C	7
Switching frequency range using RT mode		200		2000	kHz		7
Switching frequency		400	500	600	kHz	R(RT/CLK) = 400 kΩ	7
Switching frequency range using CLK mode		300		2000	kHz		7
On-resistance (PWRGD)			56	100	Ω		7
Minimum VIN for valid output			0.65	1.5	V	V(PWRGD) < 0.5 V at 100 µA	7
Input voltage, VIN pin	VIN	-0.3		7	V		5
Input voltage, EN pin	EN	-0.3		7	V		5
Input voltage, BOOT-PH	BOOT-PH			7	V		5
Input voltage, VSENSE pin	VSENSE	-0.3		3	V		5
Input voltage, COMP pin	COMP	-0.3		3	V		5
Input voltage, PWRGD pin	PWRGD	-0.3		7	V		5
Input voltage, SS/TR pin	SS/TR	-0.3		3	V		5
Input voltage, RT/CLK pin	RT/CLK	-0.3		7	V		5
Output voltage, PH pin	PH	-0.6		7	V		5
Output voltage, PH pin transient	PH	-2		10	V	10-ns transient	5
Source current, EN pin	EN			100	µA		5
Source current, RT/CLK pin	RT/CLK			100	µA		5
Source current, COMP pin	COMP			100	µA		5
Sink current, PWRGD pin	PWRGD			10	mA		5
Sink current, SS/TR pin	SS/TR			100	µA		5
Junction temperature	TJ	-55		150	°C		5
Input voltage	V(VIN)	2.95		6	V		5
Operating ambient temperature	TA	-55		125	°C		5
Operating junction temperature	TJ	-55		150	°C		5
Junction-to-ambient thermal resistance	RθJA		44.4		°C/W		6
Junction-to-case (top) thermal resistance	RθJC(top)		46.1		°C/W		6
Junction-to-board thermal resistance	RθJB		16		°C/W		6
Junction-to-case (bottom) thermal resistance	RθJC(bot)		4.6		°C/W		6

CAD (KiCad official)

Symbol: TPS57114MRTETEP
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
3D model files: tps57114mrtetep-etched.step / tps57114mrtetep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps57114mrtetep.step / tps57114mrtetep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (41 pp, sha256 fde6d5e8c2e8c768, retrieved 2026-10-30, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS57114MRTETEP

Verified TPS57114MRTETEP

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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