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TPS56920PWPR

Public Made by Adom

by adom

Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs Publish 0.1.0 · Ray 22d ago
viewers tps56920pwpr: viewers · Ray 22d ago
package.json tps56920pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
page.json tps56920pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
README.md Publish 0.1.0 · Ray 22d ago
tps56920pwpr-etched.glb tps56920pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps56920pwpr-etched.step tps56920pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps56920pwpr-hero.glb tps56920pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps56920pwpr-hero.overlay.json tps56920pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
tps56920pwpr.glb plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 17d ago
tps56920pwpr.kicad_mod Publish 0.1.0 · Ray 22d ago
tps56920pwpr.kicad_sym Publish 0.1.0 · Ray 22d ago
tps56920pwpr.lbr Publish 0.1.0 · Ray 22d ago
tps56920pwpr.step plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 17d ago

TPS56920PWPR

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS56920PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input; pull high to enable the converter.
2 SDA bidirectional I2C data I/O terminal.
3 SCL bidirectional I2C clock I/O terminal.
4 A1 input I2C chip address bit 1 (A1, A0 pins 4 and 5 set the chip address).
5 A0 input I2C chip address bit 0 (A1, A0 pins 4 and 5 set the chip address).
6 VIN power_in Supply input for the 5.5V linear regulator.
7 PVIN power_in Power input connected to the high-side MOSFET drains.
8 PVIN power_in Power input connected to the high-side MOSFET drains.
9 PGND power_in Ground return for the low-side MOSFETs; input of the current comparator.
10 PGND power_in Ground return for the low-side MOSFETs; input of the current comparator.
11 SW bidirectional Switch node for both high-side and low-side NFETs; input of the current comparator.
12 SW bidirectional Switch node for both high-side and low-side NFETs; input of the current comparator.
13 SW bidirectional Switch node for both high-side and low-side NFETs; input of the current comparator.
14 VBST power_in Supply input for the high-side NFET gate drive; connect a 0.1µF ceramic capacitor between VBST and SW.
15 PGOOD output Open-drain power-good output; low means the output is out of regulation.
16 VREG5 output Output of the 5.5V linear regulator; bypass to GND with at least 2.0µF high-quality ceramic capacitor and connect no other circuitry to it.
17 GND power_in Signal ground; connect sensitive SS and VFB returns to GND at a single point. Must be connected to the thermal pad.
18 SS output Soft-start programming terminal; connect a capacitor from SS to GND to set the soft-start time.
19 VOUT input Connection to the output voltage.
20 VFB input D-CAP2 feedback input; connect to the output voltage through a resistor divider.
21 PowerPAD power_in Exposed thermal pad on the package back side; must be soldered for proper dissipation and must be connected to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: TPS56920PWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps56920pwpr-etched.step / tps56920pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps56920pwpr.step / tps56920pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 1829a4ee99bbd0ca, retrieved 2026-10-11, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF