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tps56528ddar

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Texas Instruments DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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TPS56528DDAR

Texas Instruments · DC-DC Converters · SOIC-8-EP

TPS56528DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input control. Active-high; must be pulled up to enable the device. Held low disables the converter and puts VREG5 inactive (<10 µA shutdown current).
2 VFB input Converter feedback input. Connect to the regulated output through a resistor divider to program VOUT between 0.6 V and 7 V (internal reference ≈ 0.6 V).
3 VREG5 power_out Internal 5.5-V LDO output used to bias gate drivers and internal circuitry. Bypass with a ~0.47 µF ceramic capacitor to GND. VREG5 is not active when EN is low.
4 PG output Open-drain power-good output. Requires an external pull-up resistor. Asserted high once the regulated output is within the PG window.
5 GND power_in Device ground and power return for the low-side FET / switching current. Tie SS and VFB analog returns to GND at a single point. Bond the exposed PowerPAD to this net.
6 SW output Switch-node connection between the integrated high-side and low-side NFETs. Connect to the output inductor. DC rating -2 V to 20 V (-3 V to 22 V for 10-ns transients).
7 VBST power_in Bootstrap supply for the high-side FET gate driver. Connect a 0.1-µF ceramic capacitor between VBST and SW. An internal bootstrap diode from VREG5 refreshes this capacitor each cycle.
8 VIN power_in Main power input, 4.5 V to 18 V (absolute max 20 V). Bypass with a low-ESR ceramic capacitor as close to the pin as possible; supplies the high-side FET drain and internal LDO.
9 PowerPAD passive Exposed thermal pad on the underside of the package. Must be soldered to the PCB for thermal dissipation and electrically connected to the GND plane. Numbered 9 for schematic reference; not silkscreened as a lead.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8-EP
Category PMIC
Pins 9

Ordering variants

  • TPS56528DDAR

CAD (KiCad official)

  • Symbol: TPS56528DDAR
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: tps56528ddar-etched.step / tps56528ddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps56528ddar.step / tps56528ddar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 fa242ebffcd91af2, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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