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Ray tps565247drlr: specified limits as data (metadata.characteristics, 51 rows from the datasheet) 8bc8814 26d ago

TPS565247DRLR

Texas Instruments · DC-DC Converters · SOT-563

TPS565247DRLR from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input voltage supply pin, recommended operating range 3 V to 16 V.
2 SW output Switch node connection between high-side and low-side NFET, recommended operating range -1 V to 16 V.
3 GND power_in Ground pin serving as source terminal of low-side power NFET and ground for controller circuit, recommended operating range -0.1 V to 0.1 V.
4 AGND power_in Analog ground for internal analog circuitry, recommended operating range -0.1 V to 0.1 V, must connect to GND plane.
5 EN input Enable input to converter, recommended operating range -0.1 V to 5.5 V, driving high enables operation.
6 FB input Converter feedback input for output voltage regulation, recommended operating range -0.1 V to 5.5 V, connect through feedback resistor divider.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-563
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage (absolute maximum) VIN -0.3 18 V 4
FB, EN voltage (absolute maximum) FB, EN -0.3 6 V 4
AGND, PGND voltage (absolute maximum) AGND, PGND -0.3 0.3 V 4
Output voltage SW (absolute maximum) SW -2 18 V 4
Output voltage SW, pulse <20 ns (absolute maximum) SW (< 20 ns) -6.5 20 V < 20 ns 4
Operating junction temperature range (absolute maximum) TJ -40 150 °C 4
Storage temperature (absolute maximum) Tstg -55 150 °C 4
Input voltage (recommended) VIN 3 16 V 4
FB, EN voltage (recommended) FB, EN -0.1 5.5 V 4
AGND, PGND voltage (recommended) AGND, PGND -0.1 0.1 V 4
Output voltage SW (recommended) SW -1 16 V 4
Output voltage SW, pulse <20 ns (recommended) SW (< 20 ns) -6 18 V < 20 ns 4
Output current (recommended) IO 0 6 A 4
Operating junction temperature (recommended) TJ -40 125 °C 4
Storage temperature (recommended) Tstg -40 150 °C 4
VIN input voltage range VIN 3 16 V 5
UVLO wake-up VIN voltage UVLO 2.75 2.92 3 V Wake-up VIN voltage 5
UVLO shutdown VIN voltage UVLO 2.6 2.72 2.9 V Shutdown VIN voltage 5
FB reference voltage VREF 594 600 606 mV TJ = 25°C 5
FB reference voltage over temperature VREF 591 600 609 mV TJ = –40°C to 125°C 5
Overcurrent threshold, valley current setpoint IOCL_LS 5.3 6.9 8.5 A Valley current setpoint 5
Negative overcurrent threshold INOCL 2 3.4 4.2 A 5
EN threshold high level VEN(ON) 1.07 1.18 1.33 V 5
EN threshold low level VEN(OFF) 0.95 1 1.2 V 5
OVP trip threshold VOVP 115 120 125 % 5
UVP trip threshold VUVP 55 60 65 % 5
VIN supply current, FCCM version (TPS565247) IVIN 400 µA No load, VEN = 5 V, VFB = 0.65 V, non-switching, FCCM version 5
VIN shutdown current IINSDN 2 µA No load, VEN = 0 V 5
UVLO hysteresis VIN voltage UVLO 200 mV Hysteresis VIN voltage 5
High-side MOSFET RDS(ON) RDS(ON)HI 28.2 mΩ TJ = 25°C, VVIN ≥ 5 V 5
High-side MOSFET RDS(ON) RDS(ON)HI 30.1 mΩ TJ = 25°C, VVIN = 3 V 5
Low-side MOSFET RDS(ON) RDS(ON)LO 15.1 mΩ TJ = 25°C, VVIN ≥ 5 V 5
Low-side MOSFET RDS(ON) RDS(ON)LO 16.1 mΩ TJ = 25°C, VVIN = 3 V 5
Switching frequency FSW 600 kHz TJ = 25°C, VVOUT = 3.3 V 5
Minimum on time TON(MIN) 50 ns TJ = 25°C 5
Minimum off time TOFF(MIN) 100 ns VFB = 0.5 V 5
EN threshold hysteresis VENHYS 180 mV 5
EN pulldown resistor REN1 2 MΩ 5
Internal soft-start time tSS 1.39 ms 5
OVP prop deglitch tOVPDLY 24 µs TJ = 25°C 5
UVP prop deglitch tUVPDLY 256 µs 5
Output hiccup delay relative to SS time, UVP detect tUVPDEL 256 µs UVP detect 5
Output hiccup enable delay relative to SS time, UVP detect tUVPEN 13 ms UVP detect 5
OTP trip threshold TOTP 155 °C 5
OTP hysteresis TOTPHSY 20 °C 6
Junction-to-ambient thermal resistance RθJA 131.1 °C/W 4
Junction-to-ambient thermal resistance on EVM board (effective) RθJA_effective 58 °C/W Tested on TPS565242EVM, 2-layer, 2 oz copper, VIN = 12 V, VOUT = 5 V, IOUT = 5 A, TA = 25°C 4
Junction-to-case (top) thermal resistance RθJC(top) 45.6 °C/W 4
Junction-to-board thermal resistance RθJB 16.4 °C/W 4
Junction-to-top characterization parameter ΨJT 0.8 °C/W 4
Junction-to-board characterization parameter YJB 16.1 °C/W 4

CAD (KiCad official)

  • Symbol: TPS565247DRLR
  • Footprint: Package_TO_SOT_SMD:SOT-563
  • 3D model: SOT-563 (KiCad packages3D, STEP)
  • 3D model files: tps565247drlr-etched.step / tps565247drlr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps565247drlr.step / tps565247drlr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 3bcea8828790f320, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF