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Contents

README

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TPS56520PWPR

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS56520PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 EN input Enable input that enables the converter when pulled high (absolute maximum -0.3 V to 20 V).
2 SDA bidirectional I2C-compatible data I/O terminal (absolute maximum -0.3 V to 3.6 V).
3 SCL bidirectional I2C-compatible clock I/O terminal (absolute maximum -0.3 V to 3.6 V).
4 A1 input Chip address programming input, upper bit (absolute maximum -0.3 V to 6.5 V).
5 A0 input Chip address programming input, lower bit (absolute maximum -0.3 V to 6.5 V).
6 VIN power_in Supply input for the 5.5 V linear regulator, operating range 4.5 V to 17 V.
7 PVIN power_in Power input connected to the high-side MOSFET drains, operating range 4.5 V to 17 V; pins 7 and 8 are tied together.
8 PVIN power_in Power input connected to the high-side MOSFET drains, operating range 4.5 V to 17 V; pins 7 and 8 are tied together.
9 PGND power_in Ground return for the low-side MOSFETs and input of the current comparator; pins 9 and 10 are tied together.
10 PGND power_in Ground return for the low-side MOSFETs and input of the current comparator; pins 9 and 10 are tied together.
11 SW power_out Switch node connection for the high-side and low-side NFETs and input of the current comparator (absolute maximum -2 V to 20 V).
12 SW power_out Switch node connection for the high-side and low-side NFETs and input of the current comparator (absolute maximum -2 V to 20 V).
13 SW power_out Switch node connection for the high-side and low-side NFETs and input of the current comparator (absolute maximum -2 V to 20 V).
14 VBST power_in Supply input for the high-side NFET gate drive; connect a 0.1 µF ceramic capacitor between VBST and SW, with an internal diode to VREG5 (absolute maximum 26 V).
15 PGOOD output Open-drain power-good output that is low when the output voltage is out of regulation (sink current up to 5 mA).
16 VREG5 power_out 5.5 V linear regulator output, active when EN is high; bypass to GND with at least 2.0 µF ceramic and connect no other circuitry.
17 GND power_in Signal ground; connect the sensitive SS and VFB returns to GND at a single point.
18 SS output Soft-start programming terminal; connect a capacitor from SS to GND to set the soft-start time.
19 VOUT input Connection to the converter output voltage (absolute maximum -0.3 V to 3.6 V).
20 VFB input D-CAP2 feedback input; connect to the output voltage through a resistor divider (absolute maximum -0.3 V to 3.6 V).
21 EP power_in Exposed thermal pad on the back side that must be soldered for dissipation and connected to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: TPS56520PWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps56520pwpr-etched.step / tps56520pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps56520pwpr.step / tps56520pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 1829a4ee99bbd0ca, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF