component
TPS563206DRLR
Public Made by Adomby adom
TEXAS INSTRUMENTS Global Sourcing Parts, SOT-563-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS563206DRLR
TEXAS INSTRUMENTS · Global Sourcing Parts · SOT-563-6
TPS563206DRLR from TEXAS INSTRUMENTS, in a SOT-563-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input voltage supply pin; the recommended input voltage range is 4.2 V to 17 V (absolute maximum 18 V). |
| 2 | SW | output | Switch node connection between the high-side NFET and low-side NFET; recommended SW voltage is -1 V to 17 V (-6 V to 19 V for under 20 ns). |
| 3 | GND | power_in | Ground pin, source terminal of the low-side power NFET and ground for the controller circuit; connect the sensitive FB to this GND at a single point. |
| 4 | BST | output | Supply input for the high-side NFET gate drive circuit; connect a 0.1-µF capacitor between BST and SW (recommended BST voltage -0.1 V to 23 V). |
| 5 | EN | input | Active-high enable input that must be pulled up to enable the device; recommended input voltage range is -0.1 V to 5.5 V. |
| 6 | FB | input | Converter feedback input; connect to the output voltage through a feedback resistor divider (recommended input range -0.1 V to 5.5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | SOT-563-6 |
| Category | Global Sourcing Parts |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN | VIN | -0.3 | 18 | V | 4 | ||
| Input voltage FB, EN | FB, EN | -0.3 | 6 | V | 4 | ||
| Input voltage GND | GND | -0.3 | 0.3 | V | 4 | ||
| Output voltage BST | BST | -0.3 | 25 | V | 4 | ||
| Output voltage BST (< 20ns) | BST | -0.3 | 27 | V | < 20ns | 4 | |
| Output voltage SW | SW | -2 | 18 | V | 4 | ||
| Output voltage SW (< 20ns) | SW | -6.5 | 20 | V | < 20ns | 4 | |
| Operating Junction Temperature Range | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| Input voltage VIN | VIN | 4.2 | 17 | V | 4 | ||
| Input voltage FB, EN | FB, EN | -0.1 | 5.5 | V | 4 | ||
| Input voltage GND | GND | -0.1 | 0.1 | V | 4 | ||
| Output voltage BST | BST | -0.1 | 23 | V | 4 | ||
| Output voltage BST (< 20ns) | BST | -0.1 | 25 | V | < 20ns | 4 | |
| Output voltage SW | SW | -1 | 17 | V | 4 | ||
| Output voltage SW (< 20ns) | SW | -6 | 19 | V | < 20ns | 4 | |
| Output Current | IO | 0 | 3 | A | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Storage temperature | Tstg | -40 | 150 | °C | 4 | ||
| Vin input voltage range | Vin | 4.2 | 17 | V | 5 | ||
| Vin undervoltage lockout, wake up VIN voltage | UVLO | 3.6 | 3.8 | 4 | V | 5 | |
| Vin undervoltage lockout, shut down VIN voltage | UVLO | 3.2 | 3.4 | 3.6 | V | 5 | |
| FB voltage | VFB | 591 | 600 | 609 | mV | TJ = 25°C, Vin = 4.2, 17V | 5 |
| FB voltage | VFB | 588 | 600 | 612 | mV | TJ = -40°C to 125°C, Vin = 4.2, 17V | 5 |
| Over current threshold | IOCL_LS | 3 | 3.9 | 4.8 | A | Valley current set point | 5 |
| Negative over current threshold | INOCL | 0.7 | 1.3 | 1.9 | A | Valley current set point | 5 |
| EN threshold high-level | VEN(On) | 1.15 | 1.21 | 1.27 | V | 5 | |
| EN threshold low-level | VEN(Off) | 0.95 | 1 | 1.05 | V | 5 | |
| UVP trip threshold | VUVP | 55 | 60 | 65 | % | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 147.4 | °C/W | 5 | |||
| Junction-to-ambient thermal resistance on EVM board | RθJA_effective | 73 | °C/W | TPS563203EVM board, 2 layer, 2oz top and bottom copper, Vin = 12V, Vout = 5V, Iout = 3A, TA = 25°C | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 75.7 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 32.2 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ΨJT | 2.1 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ΨJB | 31.8 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS563206DRLR - Footprint:
Package_TO_SOT_SMD:SOT-563 - 3D model: SOT-563-6 (KiCad packages3D, STEP)
- 3D model files:
tps563206drlr-etched.step/tps563206drlr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps563206drlr.step/tps563206drlr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TEXAS INSTRUMENTS datasheet (30 pp, sha256
c47f395bebb29883, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).