component
TPS55165QPWPTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TPS55165QPWPTQ1
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
TPS55165QPWPTQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGND | power_in | Power-ground pin. |
| 2 | L1 | passive | Buck power-stage switch node; connect a nominal 4.7 µH inductor between L1 and L2. |
| 3 | BST1 | passive | Bootstrap node for the buck power stage; connect a 100-nF capacitor between this pin and L1. |
| 4 | VINP | power_in | Supply-power input voltage; connect to the input supply line. |
| 5 | VINL | power_in | Supply-input voltage for internal biasing; connect to the input supply line. |
| 6 | IGN | input | Ignition-enable input; ignition is enabled when high and disabled when low. |
| 7 | PS | input | Logic-level input that selects low-power mode when high and normal mode when low. |
| 8 | IGN_PWRL | input | Logic-level IGN power-latch signal; IGN is latched when this pin is high and not latched when low. |
| 9 | SS_EN | input | Configuration pin for spread spectrum; enabled when the pin is open and disabled when low. |
| 10 | PG_DLY | passive | Power-good delay configuration; a 10 kΩ to 100 kΩ resistor sets 0.5 ms to 40 ms, and connecting to ground gives the default 2 ms (typical). |
| 11 | VREG_Q | input | Quiet feedback pin for the gate-drive supply; connect close to the top of the 4.7-µF decoupling capacitor at VREG and always to VREG during operation to prevent EOS damage. |
| 12 | VREG | power_out | Gate-drive supply for the buck-boost power stages; needs a 4.7-µF (typical) decoupling capacitor to power ground and cannot drive external loads. |
| 13 | GND | power_in | Analog ground. |
| 14 | VOS_FB | input | On the TPS55165-Q1 this pin selects the output voltage: 5 V when connected to GND and 12 V when connected to VREG. |
| 15 | PG | output | Open-drain power-good output that is high when the status is good and low on a failure. |
| 16 | VOUT_SENSE | input | Sense pin for the buck-boost converter output voltage; must be connected to the VOUT pin. |
| 17 | VOUT | power_out | Buck-boost converter output voltage. |
| 18 | GND | power_in | Analog ground. |
| 19 | BST2 | passive | Bootstrap node for the boost power stage; connect a typical 100-nF capacitor between this pin and L2. |
| 20 | L2 | passive | Boost power-stage switch node; connect a nominal 4.7 µH inductor between L1 and L2. |
| 21 | PowerPAD | power_in | Exposed thermal pad that must be soldered to power ground to achieve the appropriate power dissipation through the analog ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage at VINP and VINL pins (after wake-up), VOS_FB to GND | 2 | 36 | V | TPS55165-Q1 with VOS_FB pin connected to GND | 5 | ||
| Supply voltage at VINP and VINL pins (after wake-up), VOS_FB to VREG | 4 | 36 | V | TPS55165-Q1 with VOS_FB pin connected to VREG | 5 | ||
| Output voltage at VOUT and VOUT_SENSE pins | 0 | 12 | V | 5 | |||
| Output voltage at PG pin | 0 | 5 | V | 5 | |||
| Input voltage on IGN pin | 0 | 36 | V | 5 | |||
| Input voltage on logic pins IGN_PWRL, PS and SS_EN | 0 | 5 | V | 5 | |||
| Input voltage on VOS_FB pin | 0 | 5 | V | TPS55165-Q1 | 5 | ||
| Operating free air temperature, TA | TA | -40 | 125 | ℃ | 5 | ||
| Operating virtual junction temperature, TJ | TJ | -40 | 150 | ℃ | 5 | ||
| Protected battery voltage | VINP, VINL | -0.3 | 40 | V | 5 | ||
| Feedback voltage | VOS_FB | -0.3 | 5.5 | V | 5 | ||
| Low-power mode input | PS | -0.3 | 40 | V | 5 | ||
| Low-voltage inputs | IGN_PWRL, SS_EN, PG_DLY | -0.3 | 5.5 | V | 5 | ||
| Ignition enable input | IGN | -7 | 40 | V | 5 | ||
| Buck-boost output voltage | VOUT, VOUT_SENSE | -0.3 | 20 | V | 5 | ||
| Gate-driver supply | VREG, VREG_Q | -0.3 | 5.5 | V | 5 | ||
| Buck switching node voltage | L1 | -0.3 | 40 | V | 5 | ||
| Boost switching node voltage | L2 | -0.3 | 20 | V | 5 | ||
| Boot-strap overdrive voltage | BST1-L1, BST2-L2 | -0.3 | 5.5 | V | 5 | ||
| Power-good output voltage | PG | -0.3 | 15 | V | 5 | ||
| Ground | PGND, GND | -0.3 | 0.3 | V | 5 | ||
| Junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 175 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 35.4 | °C/W | 6 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 0.9 | °C/W | 6 | |||
| Supply voltage operating input voltage | VIN | 2 | 14 | 36 | V | Applied at VINP and VINL pins, after device startup; TPS55165-Q1 with VOS_FB pin connected to GND | 6 |
| Supply voltage operating input voltage | VIN | 4 | 14 | 36 | V | Applied at VINP and VINL pins, after device startup; TPS55165-Q1 with VOS_FB pin connected to VREG | 6 |
| Feedback voltage in normal mode for VOUT in fixed 5-V setting | VFB_NM_5V | 4.9 | 5 | 5.1 | V | Measured at VOUT_SENSE pin; VOS_FB pin connected to GND; VOUT pin connected to VOUT_SENSE | 7 |
| Feedback voltage in normal mode for VOUT in fixed 12-V setting | VFB_NM_12V | 11.76 | 12 | 12.24 | V | Measured at VOUT_SENSE pin; VOS_FB pin connected to VREG; VOUT pin connected to VOUT_SENSE | 7 |
| Feedback voltage in low-power mode for VOUT in 5-V setting | VFB_PS_5V | 4.85 | 5 | 5.15 | V | Measured at VOUT_SENSE pin; VOS_FB pin connected to GND; VOUT pin connected to VOUT_SENSE | 7 |
| Feedback voltage in low-power mode for VOUT in 12-V setting | VFB_PS_12V | 11.64 | 12 | 12.36 | V | Measured at VOUT_SENSE pin; VOS_FB pin connected to VREG; VOUT pin connected to VOUT_SENSE | 7 |
| Pulldown discharge resistance at VOUT | RpdVOUT | 250 | 365 | 850 | Ω | Device in OFF state, INIT state, or PRE_RAMP state; VIGN = 0 V, VPS = 0 V, VIGN_PWRL = 0 V | 7 |
| Max output current in normal operation for VOUT in 5-V setting | IOUT_5V | 1 | A | TPS55165-Q1 with VOS_FB pin connected to GND; 6 V ≤ VIN; DCR ≤ 40 mΩ | 8 | ||
| Max output current in normal operation for VOUT in 5-V setting | IOUT_5V | 800 | mA | TPS55165-Q1 with VOS_FB pin connected to GND; 3.8 V ≤ VIN ≤ 6 V; DCR ≤ 40 mΩ | 8 | ||
| Max output current in normal operation for VOUT in 5-V setting | IOUT_5V | 400 | mA | TPS55165-Q1 with VOS_FB pin connected to GND; 2.3 V ≤ VIN < 3.8 V; DCR ≤ 40 mΩ | 8 | ||
| Max output current in normal operation for VOUT in 5-V setting | IOUT_5V | 200 | mA | TPS55165-Q1 with VOS_FB pin connected to GND; 2 V ≤ VIN < 2.3 V; DCR ≤ 40 mΩ | 8 | ||
| Max output current in normal operation for VOUT in 12-V setting | IOUT_12V | 800 | mA | TPS55165-Q1 with VOS_FB pin connected to VREG; 14 V ≤ VIN; DCR ≤ 40 mΩ | 8 | ||
| Max output current in normal operation for VOUT in 12-V setting | IOUT_12V | 600 | mA | TPS55165-Q1 with VOS_FB pin connected to VREG; 9.2 V ≤ VIN ≤ 14 V; DCR ≤ 40 mΩ | 8 | ||
| Max output current in normal operation for VOUT in 12-V setting | IOUT_12V | 300 | mA | TPS55165-Q1 with VOS_FB pin connected to VREG; 5.6 V ≤ VIN < 9.2 V; DCR ≤ 40 mΩ | 8 | ||
| Max output current in normal operation for VOUT in 12-V setting | IOUT_12V | 150 | mA | TPS55165-Q1 with VOS_FB pin connected to VREG; 4 V ≤ VIN < 5.6 V; DCR ≤ 40 mΩ | 8 | ||
| On-resistance buck-stage high-side (HS) FET | Rdson_BUCK_HS | 150 | 300 | mΩ | 8 | ||
| On-resistance buck-stage low-side (LS) FET | Rdson_BUCK_LS | 150 | 300 | mΩ | 8 | ||
| On-resistance boost-stage HS FET | Rdson_BOOST_HS | 150 | 300 | mΩ | 8 | ||
| On-resistance boost-stage LS FET | Rdson_BOOST_LS | 150 | 300 | mΩ | 8 | ||
| Peak current limit for HS buck, LS buck, and LS boost | ISW_limit | 2 | 3.5 | 4.5 | A | Device in normal operating mode | 8 |
| Undervoltage lockout threshold, VIN voltage decreasing, VOS_FB to GND | UVLO | 1.8 | 2 | V | Device is in normal operating mode; TPS55165-Q1 with VOS_FB pin connected to GND | 9 | |
| Undervoltage lockout threshold, VIN voltage decreasing, VOS_FB to VREG | UVLO | 3.6 | 4 | V | Device is in normal operating mode; TPS55165-Q1 with VOS_FB pin connected to VREG | 9 | |
| VIN Overvoltage (OV) lockout threshold | OVLO | 36 | 40 | V | VIN voltage increasing; Device is in normal operating mode | 9 | |
| VOUT OV protection | VOUT_PROT_OV | 110 | 125 | % | Device is in normal operating mode | 9 | |
| IGN wake-up threshold | IGNWAKE | 2.5 | 3.1 | 3.7 | V | VIGN voltage increasing to wake-up device | 9 |
| IGN power-down threshold | IGNPD | 1.5 | 2.1 | 2.7 | V | VIGN voltage decreasing to power-down device | 9 |
| IGN wake-up hysteresis | IGNHYST | 0.76 | 1 | 1.35 | V | 9 | |
| Logic input hysteresis for pins IGN_PWRL, PS, and SS_EN | VLOGIC_IN_HYST | 0.15 | 0.39 | V | Device in power-up condition | 9 | |
| Pulldown resistance on PS pin to GND | RLOGIC_IN_PD | 35 | 70 | 111 | kΩ | 9 | |
| Pullup current on SS_EN pin | Ipull-up_SS_EN | 85 | 266 | µA | 9 | ||
| Pullup current on IGN_PWRL pin | Ipull-up_IGN_PWRL | 1 | 8 | µA | 10 | ||
| Overtemperature shutdown protection threshold | TPROT | 175 | 210 | ℃ | 10 | ||
| PG threshold undervoltage, deviation from nominal VOUT to assert PG low, in normal mode | PGTH_UV | -10 | -5 | % | In normal mode | 10 | |
| PG threshold undervoltage, deviation from nominal VOUT to assert PG low, in low power mode | PGTH_UV | -20 | -5 | % | In low power mode | 10 | |
| PG deglitch filter time | PGDeglitch | 45 | 50 | 55 | µs | 12 |
CAD (KiCad official)
- Symbol:
TPS55165QPWPTQ1 - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files:
tps55165qpwptq1-etched.step/tps55165qpwptq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps55165qpwptq1.step/tps55165qpwptq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
fc2228e91106a13a, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).