TPS55162QPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PGND	power_in	Power-ground pin; the thermal pad must be soldered to the power ground.
2	L1	passive	Buck power-stage switch node; connect an inductor with a nominal value of 4.7 µH between L1 and L2.
3	BST1	passive	Bootstrap node for the buck power stage; connect a 100-nF capacitor between this pin and L1.
4	VINP	power_in	Supply-power input voltage; connect to the input supply line, with a -0.3 V to 40 V absolute maximum rating on VINP and VINL.
5	VINL	power_in	Supply-input voltage for internal biasing; connect to the input supply line, with a -0.3 V to 40 V absolute maximum rating on VINP and VINL.
6	IGN	input	Ignition-enable input; the ignition is enabled when high (1) and disabled when low (0), with an input range of 0 to 36 V.
7	PS	input	Logic-level input enabling low-power mode when high and normal mode when low, with a logic input range of 0 to 5 V.
8	IGN_PWRL	input	Logic-level IGN power-latch input; the IGN pin is latched when high (1) and not latched when low (0).
9	SS_EN	input	Spread-spectrum configuration input; the spread spectrum is enabled when this pin is open and disabled when it is low.
10	PG_DLY	input	Power-good delay configuration; a 10 kΩ to 100 kΩ resistor sets the PG delay from 0.5 ms to 40 ms, and grounding it gives the 2 ms (typical) default.
11	VREG_Q	input	Quiet feedback pin for the buck-boost gate-drive supply; it must be connected to VREG at all times during operation.
12	VREG	power_out	Gate-drive supply for the buck-boost power stages; requires a 4.7-µF (typical) decoupling capacitor and cannot drive external loads.
13	GND	power_in	Analog ground pin.
14	VOS_FB	input	For TPS55162-Q1 this pin sets VOUT through a resistive feedback network of less than 1 MΩ total resistance, with an input range of 0 to 0.8 V.
15	PG	output	Open-drain power-good output; high (1) means good and low (0) means a failure.
16	VOUT_SENSE	input	Sense pin for the buck-boost converter output voltage; it must be connected to the VOUT pin.
17	VOUT	power_out	Buck-boost converter output voltage, rated 0 V to 12 V at the VOUT and VOUT_SENSE pins.
18	GND	power_in	Analog ground pin.
19	BST2	passive	Bootstrap node for the boost power stage; connect a typical 100-nF capacitor between this pin and L2.
20	L2	passive	Boost power-stage switch node; connect an inductor with a nominal value of 4.7 µH between L1 and L2.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-20-EP
Category	Power Management (PMIC)
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Protected battery voltage VINP, VINL		-0.3		40	V		5
Feedback voltage VOS_FB		-0.3		5.5	V		5
Low-power mode input PS		-0.3		40	V		5
Low-voltage inputs IGN_PWRL, SS_EN, PG_DLY		-0.3		5.5	V		5
Ignition enable input IGN		-7		40	V		5
Buck-boost output voltage VOUT, VOUT_SENSE		-0.3		20	V		5
Gate-driver supply VREG, VREG_Q		-0.3		5.5	V		5
Buck switching node voltage L1		-0.3		40	V		5
Boost switching node voltage L2		-0.3		20	V		5
Boot-strap overdrive voltage BST1-L1, BST2-L2		-0.3		5.5	V		5
Power-good output voltage PG		-0.3		15	V		5
Ground PGND, GND		-0.3		0.3	V		5
Junction temperature	TJ	-40		150	°C		5
Supply voltage at VINP and VINL pins (after wake-up), TPS55160-Q1 and TPS55162-Q1		3.6		36	V	TPS55160-Q1 and TPS55162-Q1	5
Output voltage at VOUT and VOUT_SENSE pins		0		12	V		5
Output voltage at PG pin		0		5	V		5
Input voltage on IGN pin		0		36	V		5
Input voltage on logic pins IGN_PWRL, PS and SS_EN		0		5	V		5
Input voltage on VOS_FB pin, TPS55160/2-Q1		0		0.8	V	TPS55160/2-Q1	5
Operating free air temperature, TA		-40		125	℃		5
Operating virtual junction temperature, TJ		-40		150	℃		5
Output ceramic capacitor COUT	COUT	18	22	47	µF	Connect between VOUT and PGND	6
Value of inductor L	L	3.3	4.7	6.2	µH	Saturation current > 2.5 A, ESR < 30 mΩ	6
Value of supply input ceramic capacitor CIN	CIN	8.2	10		µF	40-V compliant. Connect between VIN and PGND	6
Decoupling capacitor on VREG pin to ground CVREG	CVREG	3.9	4.7	5.6	µF	Connect between VREG and PGND	6
Operating supply input voltage VIN	VIN	3.6	14	36	V	TPS55160/2-Q1	6
VIN shutdown supply current	ISD			3	µA	VIN = 12 V, VIGN= 0 V, VPS= 0 V, VIGN_PWRL = 0 V, TJ = 25°C	6
Feedback voltage in normal mode for adjustable VOUT setting	VFB_NM_adj	0.784	0.8	0.816	V	TPS55160/2-Q1: Measured at VOS_FB pin; resistive divider with total resistance < 1 MΩ between VOUT, VOS_FB, and GND pins	7
Feedback voltage in low-power mode for adjustable VOUT setting	VFB_PS_adj	0.776	0.8	0.824	V	TPS55160/2-Q1: Measured at VOS_FB pin; resistive divider with total resistance < 1 MΩ between VOUT, VOS_FB, and GND pins	7
Adjustable output voltage range	VOUT_OL	5.7		9	V	TPS55160/2-Q1: Measured at VOUT_SENSE pin	7
Pulldown discharge resistance at VOUT	RpdVOUT	250	365	850	Ω	Device in OFF state, INIT state, or PRE_RAMP state; VIGN = 0 V, VPS = 0 V, VIGN_PWRL = 0 V	7
Max output current in normal operation for adjustable configuration, 8V < VOUT ≤ 9V	IOUT_adj_VoutH			800	mA	TPS55160-Q1 and TPS55162-Q1, 8V < VOUT ≤ 9V; (VOUT + 2V) ≤ VIN; DCR ≤ 40 mΩ	8
Max output current in normal operation for adjustable configuration, 8V < VOUT ≤ 9V	IOUT_adj_VoutH			600	mA	TPS55160-Q1 and TPS55162-Q1, 8V < VOUT ≤ 9V; 0.76 * VOUT ≤ VIN ≤ (VOUT + 2V); DCR ≤ 40 mΩ	8
Max output current in normal operation for adjustable configuration, 8V < VOUT ≤ 9V	IOUT_adj_VoutH			300	mA	TPS55160-Q1 and TPS55162-Q1, 8V < VOUT ≤ 9V; 0.46 * VOUT ≤ VIN < 0.76 * VOUT; DCR ≤ 40 mΩ	8
Max output current in normal operation for adjustable configuration, 8V < VOUT ≤ 9V	IOUT_adj_VoutH			150	mA	TPS55160-Q1 and TPS55162-Q1, 8V < VOUT ≤ 9V; 3.6 V ≤ VIN < 0.46 * VOUT; DCR ≤ 40 mΩ	8
Max output current in normal operation for adjustable configuration, 5.7V ≤ VOUT ≤ 8V	IOUT_adj_VoutL			800	mA	TPS55160-Q1 and TPS55162-Q1, 5.7V ≤ VOUT ≤ 8V; (VOUT + 1V) ≤ VIN; DCR ≤ 40 mΩ	8
Max output current in normal operation for adjustable configuration, 5.7V ≤ VOUT ≤ 8V	IOUT_adj_VoutL			600	mA	TPS55160-Q1 and TPS55162-Q1, 5.7V ≤ VOUT ≤ 8V; 0.76 * VOUT ≤ VIN < (VOUT + 1V); DCR ≤ 40 mΩ	8
Max output current in normal operation for adjustable configuration, 5.7V ≤ VOUT ≤ 8V	IOUT_adj_VoutL			300	mA	TPS55160-Q1 and TPS55162-Q1, 5.7V ≤ VOUT ≤ 8V; 3.6 V ≤ VIN < 0.76 * VOUT; DCR ≤ 40 mΩ	8
On-resistance buck-stage high-side (HS) FET	Rdson_BUCK_HS	150		300	mΩ		8
On-resistance buck-stage low-side (LS) FET	Rdson_BUCK_LS	150		300	mΩ		8
Peak current limit for HS buck, LS buck, and LS boost	ISW_limit	2	3.5	4.5	A	Device in normal operating mode	8
Switching frequency without Spread-Spectrum	ƒSW	1860	2000	2140	kHz	VIN_max = 27 V	11
Average coil current limit	ICoilAvglimit		2	2.8	A	Device in normal operating mode; L = 4.7 µH	8
UVLO VIN undervoltage (UV) lockout threshold, TPS55160-Q1 and TPS55162-Q1	UVLO	1.8		2	V	VIN voltage decreasing; device turned-off when VIN < UVLO; device is in normal operating mode	9
OVLO VIN overvoltage (OV) lockout threshold	OVLO	36		40	V	VIN voltage increasing; device stops switching when VIN > OVLO, and recovers when VIN < OVLO and IGN = 1; device is in normal operating mode	9
VOUT OV protection	VOUT_PROT_OV	110		125	%	Device is in normal operating mode	9
IGN wake-up threshold	IGNWAKE	2.5	3.1	3.7	V	VIGN voltage increasing to wake-up device	9
IGN power-down threshold	IGNPD	1.5	2.1	2.7	V	VIGN voltage decreasing to power-down device	9
IGN wake-up hysteresis	IGNHYST	0.76	1	1.35	V		9
IGN pin forward input current at 36 V	I_IGN36V	11	17	30	µA	VIGN = 36 V	9
IGN pin forward input current at 12 V	I_IGN12V	2.3	3.7	7.1	µA	VIGN = 12 V	9
IGN pin reverse current	I_IGNrev	370	650		µA	VIGN = -7 V	9
Logic input hysteresis for pins IGN_PWRL, PS, and SS_EN	VLOGIC_IN_HYST	0.15		0.39	V	Device in power-up condition	9
PG threshold undervoltage, deviation from nominal VOUT to assert PG low in normal mode	PGTH_UV	-10		-5	%	Deviation from nominal VOUT to assert PG low, in normal mode	10
PG output-low voltage	VPG_LOW			0.4	V	IPGL ≤ 1mA	10
Overtemperature shutdown protection threshold	TPROT	175		210	℃		10
PG deglitch filter time	PGDeglitch	45	50	55	µs		12
Value of bootstrap ceramic capacitor CBST	CBST		100		nF	ESR < 10 mΩ. Connect between BST1 and L1 with respect to BST2 and L2	6
Junction-to-ambient thermal resistance	RθJA		35.4		°C/W		6

CAD (KiCad official)

Symbol: TPS55162QPWPRQ1
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
3D model files: tps55162qpwprq1-etched.step / tps55162qpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps55162qpwprq1.step / tps55162qpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (48 pp, sha256 fc2228e91106a13a, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TPS55162QPWPRQ1

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