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Ray tps54873pwpr: specified limits as data (metadata.characteristics, 50 rows from the datasheet) 7cef82b 10d ago

TPS54873PWPR

Texas Instruments · DC-DC Converters · HTSSOP-28-EP

TPS54873PWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AGND	power_in	Analog ground serving as the return for the compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin; connect the PowerPAD to AGND.
2	VSENSE	input	Error amplifier inverting input, connected to the output voltage through the compensation network/output divider.
3	COMP	output	Error amplifier output; connect the frequency compensation network from COMP to VSENSE.
4	PWRGD	output	Open-drain power good output that is high when VSENSE is at or above 90% of Vref and low otherwise, and is also low when SS/ENA is low or the internal shutdown signal is active.
5	BOOT	power_out	Bootstrap output; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver.
6	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
7	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
8	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
9	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
10	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
11	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
12	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
13	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
14	PH	output	Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor.
15	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended.
16	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended.
17	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended.
18	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended.
19	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended.
20	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor.
21	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor.
22	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor.
23	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor.
24	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor.
25	VBIAS	power_out	Internal bias regulator output supplying regulated voltage to internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
26	SS/ENA	bidirectional	Dual-function slow-start/enable pin providing a logic input to enable or disable device operation and a capacitor input to externally set the start-up time.
27	SYNC	input	Dual-function synchronization input that synchronizes to an external oscillator or selects between two internally set switching frequencies; when synchronizing externally, a resistor must be connected to the RT pin.
28	RT	input	Frequency setting resistor input; connect a resistor from RT to AGND to set the switching frequency, set at or slightly below the external oscillator frequency when SYNC is used.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-28-EP
Category	Power Supply Chip
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage range, VIN	VIN	4		6	V		3
Quiescent current, fs = 350 kHz	I(Q)	11		15.8	mA	fs = 350 kHz, SYNC ≤ 0.8 V, RT open, PH pin open	3
Quiescent current, fs = 550 kHz	I(Q)	16		23.5	mA	fs = 550 kHz, SYNC ≥ 2.5 V, RT open, PH pin open	3
Quiescent current, shutdown	I(Q)	1		1.4	mA	Shutdown, SS/ENA = 0 V	3
Start threshold voltage, UVLO		3.8		3.85	V		3
Stop threshold voltage, UVLO		3.4		3.5	V		3
Hysteresis voltage, UVLO		0.14		0.16	V		3
Output voltage, VBIAS	VBIAS	2.7	2.8	2.9	V	I(VBIAS) = 0	3
Vref accuracy	Vref	0.882	0.891	0.9	V		3
Internally set free running frequency, SYNC low		280	350	420	kHz	SYNC ≤ 0.8 V, RT open	3
Internally set free running frequency, SYNC high		440	550	660	kHz	SYNC ≥ 2.5 V, RT open	3
Externally set free running frequency, RT = 180 kΩ		252	280	308	kHz	RT = 180 kΩ (1% resistor to AGND)	3
Externally set free running frequency, RT = 100 kΩ		460	500	540	kHz	RT = 100 kΩ (1% resistor to AGND)	3
Externally set free running frequency, RT = 68 kΩ		663	700	762	kHz	RT = 68 kΩ (1% resistor to AGND)	3
Frequency range, SYNC		330		700	kHz		3
Maximum duty cycle				90	%		3
Error amplifier open loop voltage gain		90		110	dB	1 kΩ COMP to AGND	4
Error amplifier unity gain bandwidth		3		5	MHz	Parallel 10 kΩ, 160 pF COMP to AGND	4
Error amplifier common mode input voltage range		0			V	Powered by internal LDO; upper limit printed as VBIAS (not numeric)	4
Input bias current, VSENSE		60		250	nA	VSENSE = Vref	4
Output voltage slew rate (symmetric), COMP		1		1.4	V/µs		4
PWM comparator propagation delay time		70		85	ns	10-mV overdrive, excluding deadtime	4
Enable threshold voltage, SS/ENA		0.82	1.2	1.4	V		4
Internal slow-start time		2.6	3.35	4.1	ms		4
Charge current, SS/ENA		3	5	8	µA	SS/ENA = 0 V	4
Discharge current, SS/ENA		2	2.3	4	mA	SS/ENA = 1.3 V, VI = 1.5 V	4
Output saturation voltage, PWRGD		0.18		0.3	V	I(sink) = 2.5 mA	4
Current limit trip point, VI = 4.5 V		9		10	A	VI = 4.5 V, output shorted	4
Current limit trip point, VI = 6 V		11		12	A	VI = 6 V, output shorted	4
Thermal shutdown trip point		135	150	165	°C		4
Power MOSFET switches rDS(on), VI = 6 V	rDS(on)	26		47	mΩ	VI = 6 V	4
Power MOSFET switches rDS(on), VI = 4.5 V	rDS(on)	30		60	mΩ	VI = 4.5 V	4
Input voltage range, VI (VIN, SS/ENA, SYNC)	VI	-0.3		7	V		2
Input voltage range, VI (RT)	VI	-0.3		6	V		2
Input voltage range, VI (VSENSE)	VI	-0.3		4	V		2
Voltage range, BOOT		-0.3		17	V		2
Output voltage range, VO (VBIAS, COMP, PWRGD)	VO	-0.3		7	V		2
Output voltage range, VO (PH)	VO	-0.6		10	V		2
Source current, IO (COMP, VBIAS)	IO			6	mA		2
Sink current, IS (PH)	IS			12	A		2
Sink current, IS (COMP)	IS			6	mA		2
Sink current, IS (SS/ENA, PWRGD)	IS			10	mA		2
Voltage differential, AGND to PGND		-0.3		0.3	V		2
Operating virtual junction temperature range, TJ	TJ	-40		125	°C		2
Storage temperature, Tstg	Tstg	-65		150	°C		2
Lead temperature				300	°C	1.6 mm (1/16 inch) from case for 10 seconds	2
Input voltage, VI (recommended)	VI	4		6	V		2
Operating junction temperature, TJ (recommended)	TJ	-40		125	°C		2
Junction-to-ambient thermal impedance, with solder			18.2		°C/W	28-pin PWP with solder	2
Junction-to-ambient thermal impedance, without solder			40.5		°C/W	28-pin PWP without solder	2

CAD (KiCad official)

Symbol: TPS54873PWPR
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
3D model files: tps54873pwpr-etched.step / tps54873pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54873pwpr.step / tps54873pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (21 pp, sha256 dceb0d0fdbc3611f, retrieved 2026-10-12, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TPS54873PWPR

**Texas Instruments** · DC-DC Converters · HTSSOP-28-EP

TPS54873PWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground serving as the return for the compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin; connect the PowerPAD to AGND. |
| 2 | VSENSE | input | Error amplifier inverting input, connected to the output voltage through the compensation network/output divider. |
| 3 | COMP | output | Error amplifier output; connect the frequency compensation network from COMP to VSENSE. |
| 4 | PWRGD | output | Open-drain power good output that is high when VSENSE is at or above 90% of Vref and low otherwise, and is also low when SS/ENA is low or the internal shutdown signal is active. |
| 5 | BOOT | power_out | Bootstrap output; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver. |
| 6 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 7 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 8 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 9 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 10 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 11 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 12 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 13 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 14 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor. |
| 15 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended. |
| 16 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended. |
| 17 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended. |
| 18 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended. |
| 19 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND as recommended. |
| 20 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 21 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 22 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 23 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 24 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 25 | VBIAS | power_out | Internal bias regulator output supplying regulated voltage to internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. |
| 26 | SS/ENA | bidirectional | Dual-function slow-start/enable pin providing a logic input to enable or disable device operation and a capacitor input to externally set the start-up time. |
| 27 | SYNC | input | Dual-function synchronization input that synchronizes to an external oscillator or selects between two internally set switching frequencies; when synchronizing externally, a resistor must be connected to the RT pin. |
| 28 | RT | input | Frequency setting resistor input; connect a resistor from RT to AGND to set the switching frequency, set at or slightly below the external oscillator frequency when SYNC is used. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Power Supply Chip |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range, VIN | VIN | 4 |  | 6 | V |  | 3 |
| Quiescent current, fs = 350 kHz | I(Q) | 11 |  | 15.8 | mA | fs = 350 kHz, SYNC ≤ 0.8 V, RT open, PH pin open | 3 |
| Quiescent current, fs = 550 kHz | I(Q) | 16 |  | 23.5 | mA | fs = 550 kHz, SYNC ≥ 2.5 V, RT open, PH pin open | 3 |
| Quiescent current, shutdown | I(Q) | 1 |  | 1.4 | mA | Shutdown, SS/ENA = 0 V | 3 |
| Start threshold voltage, UVLO |  | 3.8 |  | 3.85 | V |  | 3 |
| Stop threshold voltage, UVLO |  | 3.4 |  | 3.5 | V |  | 3 |
| Hysteresis voltage, UVLO |  | 0.14 |  | 0.16 | V |  | 3 |
| Output voltage, VBIAS | VBIAS | 2.7 | 2.8 | 2.9 | V | I(VBIAS) = 0 | 3 |
| Vref accuracy | Vref | 0.882 | 0.891 | 0.9 | V |  | 3 |
| Internally set free running frequency, SYNC low |  | 280 | 350 | 420 | kHz | SYNC ≤ 0.8 V, RT open | 3 |
| Internally set free running frequency, SYNC high |  | 440 | 550 | 660 | kHz | SYNC ≥ 2.5 V, RT open | 3 |
| Externally set free running frequency, RT = 180 kΩ |  | 252 | 280 | 308 | kHz | RT = 180 kΩ (1% resistor to AGND) | 3 |
| Externally set free running frequency, RT = 100 kΩ |  | 460 | 500 | 540 | kHz | RT = 100 kΩ (1% resistor to AGND) | 3 |
| Externally set free running frequency, RT = 68 kΩ |  | 663 | 700 | 762 | kHz | RT = 68 kΩ (1% resistor to AGND) | 3 |
| Frequency range, SYNC |  | 330 |  | 700 | kHz |  | 3 |
| Maximum duty cycle |  |  |  | 90 | % |  | 3 |
| Error amplifier open loop voltage gain |  | 90 |  | 110 | dB | 1 kΩ COMP to AGND | 4 |
| Error amplifier unity gain bandwidth |  | 3 |  | 5 | MHz | Parallel 10 kΩ, 160 pF COMP to AGND | 4 |
| Error amplifier common mode input voltage range |  | 0 |  |  | V | Powered by internal LDO; upper limit printed as VBIAS (not numeric) | 4 |
| Input bias current, VSENSE |  | 60 |  | 250 | nA | VSENSE = Vref | 4 |
| Output voltage slew rate (symmetric), COMP |  | 1 |  | 1.4 | V/µs |  | 4 |
| PWM comparator propagation delay time |  | 70 |  | 85 | ns | 10-mV overdrive, excluding deadtime | 4 |
| Enable threshold voltage, SS/ENA |  | 0.82 | 1.2 | 1.4 | V |  | 4 |
| Internal slow-start time |  | 2.6 | 3.35 | 4.1 | ms |  | 4 |
| Charge current, SS/ENA |  | 3 | 5 | 8 | µA | SS/ENA = 0 V | 4 |
| Discharge current, SS/ENA |  | 2 | 2.3 | 4 | mA | SS/ENA = 1.3 V, VI = 1.5 V | 4 |
| Output saturation voltage, PWRGD |  | 0.18 |  | 0.3 | V | I(sink) = 2.5 mA | 4 |
| Current limit trip point, VI = 4.5 V |  | 9 |  | 10 | A | VI = 4.5 V, output shorted | 4 |
| Current limit trip point, VI = 6 V |  | 11 |  | 12 | A | VI = 6 V, output shorted | 4 |
| Thermal shutdown trip point |  | 135 | 150 | 165 | °C |  | 4 |
| Power MOSFET switches rDS(on), VI = 6 V | rDS(on) | 26 |  | 47 | mΩ | VI = 6 V | 4 |
| Power MOSFET switches rDS(on), VI = 4.5 V | rDS(on) | 30 |  | 60 | mΩ | VI = 4.5 V | 4 |
| Input voltage range, VI (VIN, SS/ENA, SYNC) | VI | -0.3 |  | 7 | V |  | 2 |
| Input voltage range, VI (RT) | VI | -0.3 |  | 6 | V |  | 2 |
| Input voltage range, VI (VSENSE) | VI | -0.3 |  | 4 | V |  | 2 |
| Voltage range, BOOT |  | -0.3 |  | 17 | V |  | 2 |
| Output voltage range, VO (VBIAS, COMP, PWRGD) | VO | -0.3 |  | 7 | V |  | 2 |
| Output voltage range, VO (PH) | VO | -0.6 |  | 10 | V |  | 2 |
| Source current, IO (COMP, VBIAS) | IO |  |  | 6 | mA |  | 2 |
| Sink current, IS (PH) | IS |  |  | 12 | A |  | 2 |
| Sink current, IS (COMP) | IS |  |  | 6 | mA |  | 2 |
| Sink current, IS (SS/ENA, PWRGD) | IS |  |  | 10 | mA |  | 2 |
| Voltage differential, AGND to PGND |  | -0.3 |  | 0.3 | V |  | 2 |
| Operating virtual junction temperature range, TJ | TJ | -40 |  | 125 | °C |  | 2 |
| Storage temperature, Tstg | Tstg | -65 |  | 150 | °C |  | 2 |
| Lead temperature |  |  |  | 300 | °C | 1.6 mm (1/16 inch) from case for 10 seconds | 2 |
| Input voltage, VI (recommended) | VI | 4 |  | 6 | V |  | 2 |
| Operating junction temperature, TJ (recommended) | TJ | -40 |  | 125 | °C |  | 2 |
| Junction-to-ambient thermal impedance, with solder |  |  | 18.2 |  | °C/W | 28-pin PWP with solder | 2 |
| Junction-to-ambient thermal impedance, without solder |  |  | 40.5 |  | °C/W | 28-pin PWP without solder | 2 |

## CAD (KiCad official)

- Symbol: `TPS54873PWPR`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `tps54873pwpr-etched.step` / `tps54873pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54873pwpr.step` / `tps54873pwpr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54873) (21 pp, sha256 `dceb0d0fdbc3611f`, retrieved 2026-10-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54873pwpr-datasheet.pdf)