# TPS54680PWPR

**Texas Instruments** · DC-DC Converters · HTSSOP-28-EP

TPS54680PWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground, the return for the compensation network/output divider, slow-start capacitor, VBIAS capacitor and RT resistor; connect the PowerPAD to AGND. |
| 2 | VSENSE | input | Error amplifier inverting input, connected to the output voltage through the compensation network/output divider; PWRGD is high when VSENSE is at or above 90% of Vref. |
| 3 | COMP | output | Error amplifier output; the frequency compensation network is connected from COMP to VSENSE. |
| 4 | PWRGD | output | Power good open-drain output that is high when VSENSE is at or above 90% of Vref and otherwise low. |
| 5 | BOOT | output | Bootstrap output; a 0.022-µF to 0.1-µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver. |
| 6 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 7 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 8 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 9 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 10 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 11 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 12 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 13 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 14 | PH | output | Phase output, the junction of the internal high-side and low-side power MOSFETs and the output inductor; all PH pins are tied together. |
| 15 | PGND | power_in | Power ground, the high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |
| 16 | PGND | power_in | Power ground, the high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |
| 17 | PGND | power_in | Power ground, the high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |
| 18 | PGND | power_in | Power ground, the high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |
| 19 | PGND | power_in | Power ground, the high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |
| 20 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 21 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 22 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 23 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 24 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 10-µF ceramic capacitor. |
| 25 | VBIAS | output | Internal bias regulator output supplying regulated voltage to internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. |
| 26 | TRACKIN | input | External reference input, a high-impedance input to the internal reference/multiplexer and error amplifier circuits. |
| 27 | ENA | input | Enable input; logic high enables the oscillator, PWM control and MOSFET driver circuits, while logic low disables operation and places the device in a low quiescent current state. |
| 28 | RT | input | Frequency setting resistor input; connect a resistor from RT to AGND to set the switching frequency. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Power Management (PMIC) |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 3 |  | 6 | V |  | 3 |
| Quiescent current | I(Q) |  | 11 | 15.8 | mA | fs = 350 kHz, RT open, PH pin open | 3 |
| Quiescent current | I(Q) |  | 16 | 23.5 | mA | fs = 500 kHz, RT = 100 kΩ, PH pin open | 3 |
| Quiescent current in shutdown | I(Q) |  | 1 | 1.4 | mA | Shutdown, ENA = 0 V | 3 |
| Start threshold voltage, UVLO |  | 2.95 |  | 3 | V |  | 3 |
| Stop threshold voltage, UVLO |  | 2.7 |  | 2.8 | V |  | 3 |
| Hysteresis voltage, UVLO |  | 0.14 |  | 0.16 | V |  | 3 |
| Output voltage, VBIAS | VBIAS | 2.7 | 2.8 | 2.9 | V | I(VBIAS) = 0 | 3 |
| Vref accuracy | Vref | 0.882 | 0.891 | 0.9 | V |  | 3 |
| Internally set free running frequency |  | 280 | 350 | 420 | kHz | RT open | 3 |
| Externally set free running frequency |  | 252 | 280 | 308 | kHz | RT = 180 kΩ (1% resistor to AGND) | 3 |
| Externally set free running frequency |  | 460 | 500 | 540 | kHz | RT = 100 kΩ (1% resistor to AGND) | 3 |
| Externally set free running frequency |  | 663 | 700 | 762 | kHz | RT = 68 kΩ (1% resistor to AGND) | 3 |
| Maximum duty cycle |  |  |  | 90 | % |  | 3 |
| Minimum controllable on time |  | 200 |  |  | ns | Specified by design | 3 |
| Error amplifier open loop voltage gain |  | 90 | 110 |  | dB | 1 kΩ COMP to AGND | 4 |
| Error amplifier unity gain bandwidth |  | 3 |  | 5 | MHz | Parallel 10 kΩ, 160 pF COMP to AGND | 4 |
| Input bias current, VSENSE |  |  | 60 | 250 | nA | VSENSE = Vref | 4 |
| Output voltage slew rate (symmetric), COMP |  | 1 |  | 1.4 | V/µs |  | 4 |
| PWM comparator propagation delay time |  | 70 |  | 85 | ns | 10-mV overdrive; PWM comparator input to PH pin (excluding deadtime) | 4 |
| Enable threshold voltage, ENA |  | 0.82 | 1.2 | 1.4 | V |  | 4 |
| Output saturation voltage, PWRGD |  |  | 0.18 | 0.3 | V | I(sink) = 2.5 mA | 4 |
| Current limit trip point |  |  | 7.2 | 10 | A | VI = 3 V, output shorted | 4 |
| Current limit trip point |  |  | 10 | 12 | A | VI = 6 V, output shorted | 4 |
| Thermal shutdown trip point |  | 135 | 150 | 165 | °C |  | 4 |
| Power MOSFET switches rDS(on) | rDS(on) |  | 26 | 47 | mΩ | VI = 6 V | 4 |
| Power MOSFET switches rDS(on) | rDS(on) |  | 36 | 65 | mΩ | VI = 3 V | 4 |
| Input offset, TRACKIN |  | -1.5 |  | 1.5 | mV | VSENSE = TRACKIN = 1.25 V | 4 |
| Input voltage range, VIN | VIN | -0.3 |  | 7 | V | VIN, ENA pins | 2 |
| Input voltage range, VI |  | -0.3 |  | 6 | V | RT pin | 2 |
| Input voltage range, VI |  | -0.3 |  | 4 | V | VSENSE, TRACKIN pins | 2 |
| Output voltage range, VO |  | -0.3 |  | 17 | V | BOOT pin | 2 |
| Output voltage range, VO |  | -0.3 |  | 7 | V | VBIAS, COMP, PWRGD pins | 2 |
| Output voltage range, VO |  | -0.6 |  | 10 | V | PH pin | 2 |
| Source current, IO | IO |  |  | 6 | mA | COMP, VBIAS pins | 2 |
| Source current, IO | IO |  |  | 12 | A | PH pin | 2 |
| Sink current, IS | IS |  |  | 6 | mA | COMP pin | 2 |
| Sink current, IS | IS |  |  | 10 | mA | ENA, PWRGD pins | 2 |
| Voltage differential AGND to PGND |  | -0.3 |  | 0.3 | V |  | 2 |
| Operating virtual junction temperature range | TJ | -40 |  | 125 | °C |  | 2 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 2 |
| Lead temperature |  |  |  | 300 | °C | 1,6 mm (1/16 inch) from case for 10 seconds | 2 |
| Input voltage | VI | 3 |  | 6 | V |  | 2 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 2 |
| Junction-to-ambient thermal impedance |  |  | 18.2 |  | °C/W | 28 Pin PWP with solder | 2 |
| Junction-to-ambient thermal impedance |  |  | 40.5 |  | °C/W | 28 Pin PWP without solder | 2 |

## CAD (KiCad official)

- Symbol: `TPS54680PWPR`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `tps54680pwpr-etched.step` / `tps54680pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54680pwpr.step` / `tps54680pwpr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54680) (23 pp, sha256 `9c8e0f15f70c2a10`, retrieved 2026-10-12, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54680pwpr-datasheet.pdf)