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TPS54613PWP

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Texas Instruments DC-DC Converters, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS54613PWP

Texas Instruments · DC-DC Converters · HTSSOP-28-EP

TPS54613PWP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground and return for the slow-start capacitor, VBIAS capacitor and RT resistor; make the PowerPAD connection to AGND.
2 VSENSE input Error amplifier inverting input; connect directly to the output voltage sense point.
3 NC unconnected No connection.
4 PWRGD output Open-drain powergood output that is high-impedance when VSENSE is at or above 90% of Vref and low otherwise; it is also low when SS/ENA is low or internal shutdown is active.
5 BOOT input Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver.
6 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
7 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
8 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
9 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
10 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
11 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
12 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
13 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
14 PH output Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together.
15 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns.
16 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns.
17 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns.
18 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns.
19 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns.
20 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
21 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
22 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
23 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
24 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
25 VBIAS power_out Internal bias regulator output supplying the internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.
26 SS/ENA bidirectional Dual-function slow-start and enable pin: a logic input enables or disables operation, and a capacitor input sets the start-up time.
27 FSEL input Frequency select logic input that selects between two internally set switching frequencies.
28 RT input Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28-EP
Category Power Supply Chip
Pins 29

CAD (KiCad official)

  • Symbol: TPS54613PWP
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: tps54613pwp-etched.step / tps54613pwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54613pwp.step / tps54613pwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 c94c631e87d000c3, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF