component
TPS54613PWP
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Texas Instruments DC-DC Converters, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+65@@ -0,0 +1,65 @@+# TPS54613PWP++**Texas Instruments** · DC-DC Converters · HTSSOP-28-EP++TPS54613PWP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog ground and return for the slow-start capacitor, VBIAS capacitor and RT resistor; make the PowerPAD connection to AGND. |+| 2 | VSENSE | input | Error amplifier inverting input; connect directly to the output voltage sense point. |+| 3 | NC | unconnected | No connection. |+| 4 | PWRGD | output | Open-drain powergood output that is high-impedance when VSENSE is at or above 90% of Vref and low otherwise; it is also low when SS/ENA is low or internal shutdown is active. |+| 5 | BOOT | input | Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver. |+| 6 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 7 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 8 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 9 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 10 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 11 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 12 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 13 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 14 | PH | output | Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together. |+| 15 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |+| 16 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |+| 17 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |+| 18 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |+| 19 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns. |+| 20 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 21 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 22 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 23 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 24 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 25 | VBIAS | power_out | Internal bias regulator output supplying the internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1-µF ceramic capacitor. |+| 26 | SS/ENA | bidirectional | Dual-function slow-start and enable pin: a logic input enables or disables operation, and a capacitor input sets the start-up time. |+| 27 | FSEL | input | Frequency select logic input that selects between two internally set switching frequencies. |+| 28 | RT | input | Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-28-EP |+| Category | Power Supply Chip |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `TPS54613PWP`+- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`+- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)+- 3D model files: `tps54613pwp-etched.step` / `tps54613pwp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54613pwp.step` / `tps54613pwp.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54612) (29 pp, sha256 `c94c631e87d000c3`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps54613pwp-datasheet.pdf)
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make the PowerPAD connection to AGND."+ },+ {+ "number": "2",+ "name": "VSENSE",+ "type": "input",+ "description": "Error amplifier inverting input; connect directly to the output voltage sense point."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection."+ },+ {+ "number": "4",+ "name": "PWRGD",+ "type": "output",+ "description": "Open-drain powergood output that is high-impedance when VSENSE is at or above 90% of Vref and low otherwise; it is also low when SS/ENA is low or internal shutdown is active."+ },+ {+ "number": "5",+ "name": "BOOT",+ "type": "input",+ "description": "Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver."+ },+ {+ "number": "6",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "7",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "8",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "9",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "10",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "11",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "12",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "13",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "14",+ "name": "PH",+ "type": "output",+ "description": "Phase switching node, the junction of the internal high-side and low-side power MOSFETs and the output inductor; tie all PH pins together."+ },+ {+ "number": "15",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns."+ },+ {+ "number": "16",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns."+ },+ {+ "number": "17",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns."+ },+ {+ "number": "18",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns."+ },+ {+ "number": "19",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns."+ },+ {+ "number": "20",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "21",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "22",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "23",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "24",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V; bypass to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "25",+ "name": "VBIAS",+ "type": "power_out",+ "description": "Internal bias regulator output supplying the internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1-µF ceramic capacitor."+ },+ {+ "number": "26",+ "name": "SS/ENA",+ "type": "bidirectional",+ "description": "Dual-function slow-start and enable pin: a logic input enables or disables operation, and a capacitor input sets the start-up time."+ },+ {+ "number": "27",+ "name": "FSEL",+ "type": "input",+ "description": "Frequency select logic input that selects between two internally set switching frequencies."+ },+ {+ "number": "28",+ "name": "RT",+ "type": "input",+ "description": "Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The MPN TPS54613PWP does not appear in the datasheet's Package Option Addendum (page 20). The addend; The exposed PowerPAD (thermal pad) is shown in the pin diagram and referenced in the text (connect t; The datasheet is a family datasheet covering TPS54611 through TPS54616. The pin table on page 3 appl",+ "exposed pad 29 added from the footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0946,+ "at": "2026-10-08T19:13:24"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps54612",+ "pages": 29,+ "sha256": "c94c631e87d000c3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps54613pwp.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.2,+ 9.7,+ 1.05+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ff242f1d3be9d09e7f929707a2c5b1ee974a4f882053b04bcdb1cd2cb21223ef",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps54613pwp-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7.2,+ 9.7,+ 1.05+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ef578da075b417a802450cf0ebdee1fa7d10afb3f49276480b36ded5495ca568",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}