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TPS54612PWPR

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Texas Instruments DC-DC Converters, TSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps54612pwprfactory-2.0.0extractor-text

Verified TPS54612PWPR

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 29 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS54612PWPR · TSSOP-28-EP · 29 pins
  • ✓copper: 29 copper pads, none touching another net
  • ✓datasheet: all 29 pin names found in the 26-page datasheet
  • ✓distributor: lcsc C575547, digikey 296-37447-2-ND, mouser 595-TPS54612PWPR
  • ✓family: TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-nrf4omi4/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 29 pins = 29 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 29 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps54612pwpr.kicad_sym✓ tps54612pwpr.kicad_mod✓ tps54612pwpr.step
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TPS54612PWPR

Texas Instruments · DC-DC Converters · TSSOP-28-EP

TPS54612PWPR from Texas Instruments, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground that serves as the return for the slow-start capacitor, VBIAS capacitor and RT resistor, and must be connected to the PowerPAD.
2 VSENSE input Error amplifier inverting input that must connect directly to the output voltage sense point.
3 NC unconnected No connection.
4 PWRGD output Open-drain powergood output that is high-Z when VSENSE is at or above 90% of Vref and low otherwise, and is low when SS/ENA is low or internal shutdown is active.
5 BOOT input Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor from BOOT to PH generates the floating drive for the high-side FET driver.
6 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
7 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
8 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
9 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
10 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
11 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
12 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
13 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
14 PH output Phase node at the junction of the internal high-side and low-side power MOSFETs and the output inductor, rated −0.6 V to 10 V.
15 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET and should connect to large copper areas.
16 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET and should connect to large copper areas.
17 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET and should connect to large copper areas.
18 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET and should connect to large copper areas.
19 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET and should connect to large copper areas.
20 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF ceramic capacitor.
21 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF ceramic capacitor.
22 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF ceramic capacitor.
23 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF ceramic capacitor.
24 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a 1-µF to 10-µF ceramic capacitor.
25 VBIAS power_out Internal bias regulator output that supplies internal circuitry and must be bypassed to AGND with a 0.1-µF to 1-µF low-ESR ceramic capacitor.
26 SS/ENA bidirectional Dual-function slow-start and enable pin that provides a logic input to enable or disable operation and a capacitor input to set start-up time.
27 FSEL input Frequency select logic input that selects between two internally set switching frequencies.
28 RT input Frequency setting resistor input; connect a resistor from RT to AGND to set the switching frequency.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-28-EP
Category Power Management (PMIC)
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 3 6 V 5
Controller input voltage VIN 3 6 V Recommended operating range 4
Junction temperature TJ -40 125 °C 4
Input voltage VIN, SS/ENA, FSEL -0.3 7 V 4
Input voltage RT -0.3 6 V 4
Input voltage VSENSE -0.3 4 V 4
Input voltage BOOT -0.3 17 V 4
Output voltage VBIAS, PWRGD -0.3 7 V 4
Output voltage PH -0.6 10 V 4
Voltage differential AGND to PGND -0.3 0.3 V 4
Sink current PH 12 A 4
Source current VBIAS 6 mA 4
Sink current SS/ENA, PWRGD 10 mA 4
Operating virtual junction temperature TJ -40 125 °C 4
Storage temperature Tstg -65 150 °C 4
Quiescent current I(Q) 6.2 9.6 mA fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open 5
Quiescent current I(Q) 8.4 12.8 mA fs = 550 kHz, FSEL ≤ 2.5 V, RT open, phase pin open 5
Shutdown current I(Q) 1 1.4 mA Shutdown, SS/ENA = 0 V 5
Start threshold voltage UVLO 2.95 3 V 5
Stop threshold voltage UVLO 2.7 2.8 V 5
Hysteresis voltage UVLO 0.14 0.16 V 5
Output voltage VBIAS 2.7 2.8 2.9 V I(VBIAS) = 0 5
Output voltage TPS54612 VO 1.2 V TJ = 25°C, VIN = 5 V 5
Output voltage tolerance TPS54612 VO -2 2 % 3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, −40°C ≤ TJ ≤ 125°C 5
Internally set oscillator frequency fs 280 350 420 kHz FSEL ≤ 0.8 V, RT open 5
Internally set oscillator frequency fs 440 550 660 kHz FSEL ≥ 2.5 V, RT open 5
Externally set oscillator frequency fs 252 280 308 kHz RT = 180 kΩ (1% resistor to AGND) 5
Externally set oscillator frequency fs 460 500 540 kHz RT = 100 kΩ (1% resistor to AGND) 5
Externally set oscillator frequency fs 663 700 762 kHz RT = 68 kΩ (1% resistor to AGND) 5
PWM comparator propagation delay 70 85 ns 10-mV overdrive (excluding deadtime) 6
Enable threshold voltage SS/ENA 0.82 1.2 1.4 V 6
Internal slow-start time TPS54612 3.5 4.5 5.4 ms 6
Charge current SS/ENA 3 5 8 µA SS/ENA = 0V 6
Discharge current SS/ENA 1.5 2.3 4 mA SS/ENA = 0.2 V, VI = 2.7 V 6
Output saturation voltage PWRGD 0.18 0.3 V I(sink) = 2.5 mA 6
Current limit at VI = 3 V 7.2 10 A VI = 3 V 6
Current limit at VI = 6 V 10 12 A VI = 6 V 6
Current limit leading edge blanking time 100 ns 6
Current limit total response time 200 ns 6
Thermal shutdown trip point 135 150 165 °C 6
Power MOSFET switches rDS(on) rDS(on) 26 47 mΩ IO = 3 A, VI = 6 V 6
Power MOSFET switches rDS(on) rDS(on) 36 65 mΩ IO = 3 A, VI = 3 V 6
Junction-to-ambient thermal resistance, with solder RθJA 18.2 °C/W PWP (28 pins), 4-layer test board 4
Junction-to-ambient thermal resistance, without solder RθJA 40.5 °C/W PWP (28 pins), 4-layer test board 4
Power dissipation rating, with solder 5.49 W TA = 25°C, 28-pin PWP with solder 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper copper areas to the input and output supply returns, and negative terminals of the input and output 3

CAD (KiCad official)

  • Symbol: TPS54612PWPR
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: tps54612pwpr-etched.step / tps54612pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54612pwpr.step / tps54612pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 bd993d34da5aaf2a, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF