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TPS54561QDPRRQ1
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Texas Instruments Pre-ordered Chips, WSON-10-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS54561QDPRRQ1
Texas Instruments · Pre-ordered Chips · WSON-10-EP(4x4)
TPS54561QDPRRQ1 from Texas Instruments, in a WSON-10-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap capacitor connects between BOOT and SW; if its voltage falls below the minimum needed for the high-side MOSFET, the gate driver switches off until the capacitor recharges. |
| 2 | VDD | power_in | Input supply pin with a 4.5-V to 60-V operating range. |
| 3 | EN | input | Enable pin with internal pullup current source; pull below 1.2 V to disable, float to enable, and use two resistors to adjust the input undervoltage lockout. |
| 4 | SS/TR | input | Soft-start and tracking input where an external capacitor sets the output rise time, and a voltage on the pin overrides the internal reference for tracking and sequencing. |
| 5 | RT/CLK | input | Resistor timing and external clock pin: a resistor to ground sets the switching frequency, and pulling it above the PLL upper threshold makes it a high-impedance synchronization clock input to the internal PLL. |
| 6 | FB | input | Inverting input of the transconductance (gm) error amplifier. |
| 7 | COMP | output | Error amplifier output and input to the output switch-current (PWM) comparator; frequency compensation components connect to this pin. |
| 8 | GND | power_in | Ground pin, which must be electrically connected to the copper pad under the IC on the printed circuit board. |
| 9 | SW | power_out | Source of the internal high-side power MOSFET and switching node of the converter. |
| 10 | PWRGD | output | Open-drain power-good output that asserts if the output voltage is low because of thermal shutdown, dropout, overvoltage, or EN shutdown. |
| 11 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-10-EP(4x4) |
| Category | Interface ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Internal undervoltage lockout threshold | 4.1 | 4.3 | 4.48 | V | VDD rising | 5 | |
| Operating input voltage | VDD | 4.5 | 60 | V | 5 | ||
| Shutdown supply current | 2.25 | 4.5 | µA | V(EN) = 0 V, TA = 25°C, 4.5 V ≤ VDD ≤ 60 V | 5 | ||
| Operating: nonswitching supply current | 152 | 200 | µA | V(FB) = 0.9 V, TA = 25°C | 5 | ||
| Enable threshold voltage | V(EN)th | 1.1 | 1.2 | 1.3 | V | No voltage hysteresis, rising and falling | 5 |
| Enable input current | -1.8 | -1.2 | -0.58 | µA | Enable threshold, 50 mV | 5 | |
| Hysteresis current | I(HYS) | -4.5 | -3.4 | -2.2 | µA | 5 | |
| Voltage reference | Vref | 0.792 | 0.8 | 0.808 | V | 5 | |
| High-side MOSFET on-resistance | 87 | 185 | mΩ | VDD = 12 V, V(BOOT-SW) = 6 V | 5 | ||
| Current limit threshold | 6.3 | 7.5 | 8.8 | A | All VDD and temperatures, open loop | 5 | |
| Current limit threshold | 6.3 | 7.5 | 8.3 | A | All temperatures, VDD = 12 V, open loop | 5 | |
| Current limit threshold | 7.1 | 7.5 | 7.9 | A | VDD = 12 V, TA = 25°C, open loop | 5 | |
| RT/CLK high threshold | 1.55 | 2 | V | 6 | |||
| RT/CLK low threshold | 0.5 | 1.2 | V | 6 | |||
| Minimum input voltage for defined output voltage | 0.9 | 2 | V | V(PWRGD) < 0.5 V, I(PWRGD) = 100 µA | 6 | ||
| Minimum CLK input pulse duration | 15 | ns | 6 | ||||
| Enable to COMP active | 540 | µs | VDD = 12 V, TA = 25°C | 6 | |||
| Switching frequency | f(SW) | 450 | 500 | 550 | kHz | R(RT) = 200 kΩ | 6 |
| Switching frequency range using RT mode | 100 | 2500 | kHz | 6 | |||
| Switching frequency range using CLK mode | 160 | 2300 | kHz | 6 | |||
| Input voltage VDD | VDD | -0.3 | 65 | V | 4 | ||
| Input voltage EN | EN | -0.3 | 8.4 | V | 4 | ||
| Input voltage FB | FB | -0.3 | 3 | V | 4 | ||
| Input voltage COMP | COMP | -0.3 | 3 | V | 4 | ||
| Input voltage PWRGD | PWRGD | -0.3 | 6 | V | 4 | ||
| Input voltage SS/TR | SS/TR | -0.3 | 3 | V | 4 | ||
| Input voltage RT/CLK | RT/CLK | -0.3 | 3.6 | V | 4 | ||
| Output voltage BOOT-SW | BOOT-SW | -0.3 | 8 | V | 4 | ||
| Output voltage SW | SW | -0.6 | 65 | V | 4 | ||
| Output voltage SW, 5-ns transient | SW | -7 | 65 | V | 5-ns transient | 4 | |
| Output voltage SW, 10-ns transient | SW | -2 | 65 | V | 10-ns transient | 4 | |
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human-body model, per AEC Q100-002 | 4 | |
| ESD CDM | V(ESD) | -750 | 750 | V | Charged-device model, per AEC-Q100-011 | 4 | |
| Supply input voltage | VDD | 4.5 | 60 | V | 4 | ||
| Output voltage | VO | 0.8 | 58.8 | V | 4 | ||
| Output current | IO | 0 | 5 | A | 4 | ||
| Junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 35.1 | °C/W | standard board | 5 | ||
| Junction-to-case (top) thermal resistance | RθJCtop | 34.1 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 12.3 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 0.3 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 12.5 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJCbot | 2.2 | °C/W | 5 | |||
| Thermal shutdown | 176 | °C | 5 | ||||
| Thermal shutdown hysteresis | 12 | °C | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | To ensure proper operation, electrically connect the GND pin to the copper pad under the IC on the printed | 3 |
CAD (KiCad official)
- Symbol:
TPS54561QDPRRQ1 - Footprint:
Package_SON:WSON-10-1EP_4x4mm_P0.8mm_EP2.6x3mm - 3D model: WSON-10-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps54561qdprrq1-etched.step/tps54561qdprrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54561qdprrq1.step/tps54561qdprrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
6999bc04acb346ca, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).