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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206

Name	Last commit message	Last updated
docs	tps54560ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
viewers	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
package.json	Publish 0.2.0 · Ray	1mo ago
pads.json	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
page.json	Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray	11d ago
README.md	tps54560ddar: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	17d ago
tps54560ddar-etched.fit.json	tps54560ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
tps54560ddar-etched.glb	tps54560ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
tps54560ddar-etched.step	tps54560ddar: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
tps54560ddar.glb	fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> TI_SO-PowerPAD-8 (ep_dropped, 8 pins; datasheet EP 2.71x3.4mm, land 2.41x3.1mm (Δ0.6mm)) · Ray	1mo ago
tps54560ddar.kicad_mod	fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> TI_SO-PowerPAD-8 (ep_dropped, 8 pins; datasheet EP 2.71x3.4mm, land 2.41x3.1mm (Δ0.6mm)) · Ray	1mo ago
tps54560ddar.kicad_sym	Publish 0.1.0 · Ray	1mo ago
tps54560ddar.lbr	rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 0 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray	1mo ago
tps54560ddar.step	fix footprint: SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm -> TI_SO-PowerPAD-8 (ep_dropped, 8 pins; datasheet EP 2.71x3.4mm, land 2.41x3.1mm (Δ0.6mm)) · Ray	1mo ago

TPS54560DDAR

Texas Instruments · DC-DC Converters · SOIC-8-EP

TPS54560DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT	passive	Bootstrap capacitor node for high-side MOSFET gate drive. A bootstrap capacitor is required between BOOT and SW; if the voltage on this capacitor falls below the minimum required to operate the high-side MOSFET, the output is switched off until the capacitor is refreshed. BOOT-SW absolute maximum is 8 V.
2	VIN	power_in	Input supply voltage with 4.5 V to 60 V operating range (absolute maximum 65 V). Provides power to the internal high-side MOSFET and control circuitry.
3	EN	input	Enable input with internal pull-up current source (~1.2 µA). Pull below 1.2 V to disable; float to enable. Can be used with two resistors to program input undervoltage lockout. Absolute maximum 8.4 V.
4	RT/CLK	bidirectional	Resistor Timing and External Clock input. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency (100 kHz to 2.5 MHz). If pulled above the PLL upper threshold, the terminal becomes a synchronization clock input (160 kHz to 2.3 MHz). Absolute maximum 3.6 V.
5	FB	input	Inverting input of the transconductance (gm) error amplifier. Regulates to the internal 0.8 V reference. Absolute maximum 3 V.
6	COMP	output	Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency compensation components (Type-II RC network) between COMP and GND. Absolute maximum 3 V.
7	GND	power_in	Device ground reference. Must be connected to the exposed thermal pad on the PCB for proper operation.
8	SW	power_out	Source of the internal high-side power MOSFET and switching node of the converter. Connect to the output inductor and catch (Schottky) diode. Absolute maximum -0.6 V to 65 V (-2 V for 10 ns transients).
9	Thermal Pad	power_in	Exposed thermal pad on the bottom of the package. Must be electrically connected to the GND terminal on the PCB and to a copper heat-sinking area for proper thermal and electrical operation.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8-EP
Category	PMIC
Pins	9

Ordering variants

Same part, different packaging or reel option.

TPS54560DDAR

CAD (KiCad official)

Symbol: TPS54560DDAR
Footprint: Package_SO:TI_SO-PowerPAD-8
3D model: SOIC-8-EP (KiCad packages3D, STEP)
3D model files: tps54560ddar-etched.step / tps54560ddar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54560ddar.step / tps54560ddar.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`tps54560ddar.step`	123 KB	You want the bare part, or you mark your own boards.
`tps54560ddar-etched.step`	2.5 MB	You want the part with `TPS54560DDAR` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 620 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (46 pp, sha256 0ac3f17dc0fba7b9, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF