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tps54519rter

Public Made by Adom

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Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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TPS54519RTER

Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)

TPS54519RTER from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PH power_out Switch node. Source of the internal high-side power MOSFET and drain of the internal low-side (synchronous) rectifier MOSFET. Connect to output inductor. Absolute max: -0.6 V to 7 V (transient -2 V to 7 V for 10 ns). Tied together with pins 10, 11, 12.
2 VIN power_in Input supply voltage, 2.95 V to 6 V (abs max 7 V). Bypass locally to GND. Tied together with pins 1(VIN pins 2 and 16 per pinout). Shared with pins 16.
3 GND power_in Power ground. Return for the internal low-side MOSFET. Must be connected directly to the exposed PowerPAD under the IC. Tied together with pin 4.
4 GND power_in Power ground. Return for the internal low-side MOSFET. Must be connected directly to the exposed PowerPAD under the IC. Tied together with pin 3.
5 AGND power_in Analog ground. Reference for internal analog circuitry. Should be electrically connected to GND close to the device.
6 VSENSE input Inverting input of the transconductance (gm) error amplifier. Connect to the feedback resistor divider from VOUT. Regulates to 0.6 V ±1%. Abs max -0.3 V to 3 V; input bias current ~50 nA.
7 COMP output Error amplifier output and input to the output-switch current comparator. Connect frequency-compensation network (typ. series R-C to AGND) here. Abs max -0.3 V to 3 V; sink current 100 µA.
8 RT input Resistor Timing. A resistor from RT to AGND sets the switching frequency between 200 kHz and 2 MHz (e.g. 84 kΩ → ~490 kHz). Abs max -0.3 V to 6 V; source current 100 µA.
9 SS/TR input Slow-start / tracking. An external capacitor sets the output-voltage rise time (charge current ~2.4 µA at V(SS)=0.3 V). Can also be driven by an external ramp for output tracking/sequencing. Abs max -0.3 V to 3 V.
10 PH power_out Switch node. Source of the internal high-side MOSFET and drain of the low-side (synchronous) MOSFET. Tied together with pins 1, 11, 12; connect to the output inductor.
11 PH power_out Switch node. Source of the internal high-side MOSFET and drain of the low-side (synchronous) MOSFET. Tied together with pins 1, 10, 12; connect to the output inductor.
12 PH power_out Switch node. Source of the internal high-side MOSFET and drain of the low-side (synchronous) MOSFET. Tied together with pins 1, 10, 11; connect to the output inductor.
13 BOOT power_in High-side gate driver bootstrap. Connect a ceramic bootstrap capacitor between BOOT and PH. BOOT-PH abs max 8 V. If VBOOT-PH falls below the BOOT UVLO (~2.1 V typ, 2.75 V max), switching is inhibited until the cap is refreshed.
14 PWRGD output Open-drain Power Good output. Pulls low during thermal shutdown, over-current, over/under-voltage on VSENSE (asserts good at 93% Vref, fault at 110% Vref, 2% hysteresis), or when EN is low. Abs max -0.3 V to 7 V; sink 10 mA. Requires external pull-up.
15 EN input Enable input with internal pull-up current source. Pull below 1.18 V (falling) to disable; float or pull above 1.25 V (rising) to enable. External resistor divider from VIN can program an adjustable input UVLO. Abs max -0.3 V to 7 V.
16 VIN power_in Input supply voltage, 2.95 V to 6 V (abs max 7 V). Bypass locally to GND. Tied together with pin 2.
17 PowerPAD power_in Exposed thermal pad on the bottom of the QFN package. Must be soldered to the PCB ground plane using multiple thermal vias for proper thermal performance. Electrically connected to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category PMIC
Pins 17

Ordering variants

  • TPS54519RTER
  • TPS54519RTERRTET

CAD (KiCad official)

  • Symbol: TPS54519RTER
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps54519rter-etched.step / tps54519rter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54519rter.step / tps54519rter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (None pp, sha256 8737d50edc7b55d4, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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Datasheet

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