component
TPS54495PWPR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54495PWPR
Texas Instruments · DC-DC Converters · HTSSOP-16-EP
TPS54495PWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN1 | power_in | Power input connected to the channel 1 high-side NFET drain; the datasheet gives a recommended input range of 4.5 V to 18 V and an absolute maximum of -0.3 V to 20 V. |
| 2 | VBST1 | power_in | Bootstrap supply input for the channel 1 high-side NFET gate drive; connect a 0.1 µF ceramic capacitor between VBST1 and SW1 (internal diode from VREG5 to VBST1). |
| 3 | SW1 | bidirectional | Channel 1 switch node for the high-side and low-side NFETs and input of the channel 1 current comparator; absolute maximum range is -2 V to 20 V (-3 V to 22 V for 10 ns transients). |
| 4 | PGND1 | power_in | Ground return for the channel 1 low-side MOSFET and input of the channel 1 current comparator. |
| 5 | EN1 | input | Channel 1 enable input; pull high to enable the converter, with an H-level threshold of 2.0 V and an L-level threshold of 0.4 V. |
| 6 | SS1 | output | Channel 1 soft-start programming pin; connect a capacitor from SS1 to GND to set the soft-start time. |
| 7 | VFB1 | input | Channel 1 D-CAP2 feedback input, connected to the output voltage through a resistor divider; absolute maximum range is -0.3 V to 6.5 V. |
| 8 | GND | power_in | Signal ground; connect the sensitive SS1, SS2, VFB1 and VFB2 returns to GND at a single point. |
| 9 | VREG5 | power_out | Output of the 5.5 V linear regulator, active when VIN1 is applied; bypass to GND with a high-quality ceramic capacitor of at least 1 µF. |
| 10 | VFB2 | input | Channel 2 D-CAP2 feedback input, connected to the output voltage through a resistor divider; absolute maximum range is -0.3 V to 6.5 V. |
| 11 | SS2 | output | Channel 2 soft-start programming pin; connect a capacitor from SS2 to GND to set the soft-start time. |
| 12 | EN2 | input | Channel 2 enable input; pull high to enable the converter, with an H-level threshold of 2.0 V and an L-level threshold of 0.4 V. |
| 13 | PGND2 | power_in | Ground return for the channel 2 low-side MOSFET and input of the channel 2 current comparator. |
| 14 | SW2 | bidirectional | Channel 2 switch node for the high-side and low-side NFETs and input of the channel 2 current comparator; absolute maximum range is -2 V to 20 V (-3 V to 22 V for 10 ns transients). |
| 15 | VBST2 | power_in | Bootstrap supply input for the channel 2 high-side NFET gate drive; connect a 0.1 µF ceramic capacitor between VBST2 and SW2 (internal diode from VREG5 to VBST2). |
| 16 | VIN2 | power_in | Power input for the channel 2 high-side NFET drain and supply input for the 5.5 V linear regulator; the datasheet gives a recommended input range of 4.5 V to 18 V and an absolute maximum of -0.3 V to 20 V. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Management (PMIC) |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
TPS54495PWPR - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
tps54495pwpr-etched.step/tps54495pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54495pwpr.step/tps54495pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
361dbe796e8ec0a7, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).