component
TPS54427DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -39,6 +39,20 @@ TPS54427DDAR from Texas Instruments, in a SOP-8. Pinout and pin descriptions ext - Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm` - 3D model: SOP-8 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`tps54427ddar.step`](tps54427ddar.step) | 123 KB | You want the bare part, or you mark your own boards. |+| [`tps54427ddar-etched.step`](tps54427ddar-etched.step) | 2.2 MB | You want the part with `TPS54427DDAR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 558 faces against 147 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "tps54427ddar",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "Texas Instruments DC-DC Converters, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+11−11@@ -4,7 +4,7 @@ "slug": "tps54427ddar", "title": "TPS54427DDAR", "brief": "Texas Instruments DC-DC Converters, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,25 +34,25 @@ "number": "1", "name": "EN", "type": "input",- "description": "Enable input control. Active high; must be pulled up to enable the device. VIH \u2265 1.6 V, VIL \u2264 0.6 V. Internal ~450 k\u03a9 pull-down to GND (225-900 k\u03a9). Absolute max \u22120.3 to 20 V."+ "description": "Enable input control. Active high; must be pulled up to enable the device. VIH ≥ 1.6 V, VIL ≤ 0.6 V. Internal ~450 kΩ pull-down to GND (225-900 kΩ). Absolute max −0.3 to 20 V." }, { "number": "2", "name": "VFB", "type": "input",- "description": "Converter feedback input. Connect to the output voltage via a resistor divider to set VOUT. Internal reference (VFBTH) is 765 mV typ (757-773 mV at 25 \u00b0C). Input current \u00b10.1 \u00b5A max."+ "description": "Converter feedback input. Connect to the output voltage via a resistor divider to set VOUT. Internal reference (VFBTH) is 765 mV typ (757-773 mV at 25 °C). Input current ±0.1 µA max." }, { "number": "3", "name": "VREG5", "type": "power_out",- "description": "5.5 V internal LDO power supply output (5.2-5.7 V, up to 60 mA). Bypass with a ~1 \u00b5F capacitor to GND. Not active when EN is low. Also feeds internal gate drive."+ "description": "5.5 V internal LDO power supply output (5.2-5.7 V, up to 60 mA). Bypass with a ~1 µF capacitor to GND. Not active when EN is low. Also feeds internal gate drive." }, { "number": "4", "name": "SS", "type": "input",- "description": "Soft-start control. Connect an external capacitor from SS to GND to program the soft-start ramp time. Absolute max \u22120.3 to 6.5 V."+ "description": "Soft-start control. Connect an external capacitor from SS to GND to program the soft-start ramp time. Absolute max −0.3 to 6.5 V." }, { "number": "5",@@ -64,13 +64,13 @@ "number": "6", "name": "SW", "type": "power_out",- "description": "Switch node between the high-side NFET (drain of low-side, source of high-side). Connect to the output inductor. Absolute max \u22122 to 20 V (\u22123 to 22 V for 10 ns transients)."+ "description": "Switch node between the high-side NFET (drain of low-side, source of high-side). Connect to the output inductor. Absolute max −2 to 20 V (−3 to 22 V for 10 ns transients)." }, { "number": "7", "name": "VBST", "type": "power_in",- "description": "Bootstrap supply for the high-side FET gate driver. Connect a 0.1 \u00b5F capacitor between VBST and SW. An internal diode is connected between VREG5 and VBST for charging. VBST(vs SW) max 6 V."+ "description": "Bootstrap supply for the high-side FET gate driver. Connect a 0.1 µF capacitor between VBST and SW. An internal diode is connected between VREG5 and VBST for charging. VBST(vs SW) max 6 V." }, { "number": "8",@@ -156,9 +156,9 @@ "docs/hero.png", "docs/tps54427ddar-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "Texas Instruments DC-DC Converters, SOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D." }