component
TPS54427DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+10−7@@ -32,25 +32,25 @@ "number": "1", "name": "EN", "type": "input",- "description": "Enable input control. Active high; must be pulled up to enable the device. VIH \u2265 1.6 V, VIL \u2264 0.6 V. Internal ~450 k\u03a9 pull-down to GND (225-900 k\u03a9). Absolute max \u22120.3 to 20 V."+ "description": "Enable input control. Active high; must be pulled up to enable the device. VIH ≥ 1.6 V, VIL ≤ 0.6 V. Internal ~450 kΩ pull-down to GND (225-900 kΩ). Absolute max −0.3 to 20 V." }, { "number": "2", "name": "VFB", "type": "input",- "description": "Converter feedback input. Connect to the output voltage via a resistor divider to set VOUT. Internal reference (VFBTH) is 765 mV typ (757-773 mV at 25 \u00b0C). Input current \u00b10.1 \u00b5A max."+ "description": "Converter feedback input. Connect to the output voltage via a resistor divider to set VOUT. Internal reference (VFBTH) is 765 mV typ (757-773 mV at 25 °C). Input current ±0.1 µA max." }, { "number": "3", "name": "VREG5", "type": "power_out",- "description": "5.5 V internal LDO power supply output (5.2-5.7 V, up to 60 mA). Bypass with a ~1 \u00b5F capacitor to GND. Not active when EN is low. Also feeds internal gate drive."+ "description": "5.5 V internal LDO power supply output (5.2-5.7 V, up to 60 mA). Bypass with a ~1 µF capacitor to GND. Not active when EN is low. Also feeds internal gate drive." }, { "number": "4", "name": "SS", "type": "input",- "description": "Soft-start control. Connect an external capacitor from SS to GND to program the soft-start ramp time. Absolute max \u22120.3 to 6.5 V."+ "description": "Soft-start control. Connect an external capacitor from SS to GND to program the soft-start ramp time. Absolute max −0.3 to 6.5 V." }, { "number": "5",@@ -62,13 +62,13 @@ "number": "6", "name": "SW", "type": "power_out",- "description": "Switch node between the high-side NFET (drain of low-side, source of high-side). Connect to the output inductor. Absolute max \u22122 to 20 V (\u22123 to 22 V for 10 ns transients)."+ "description": "Switch node between the high-side NFET (drain of low-side, source of high-side). Connect to the output inductor. Absolute max −2 to 20 V (−3 to 22 V for 10 ns transients)." }, { "number": "7", "name": "VBST", "type": "power_in",- "description": "Bootstrap supply for the high-side FET gate driver. Connect a 0.1 \u00b5F capacitor between VBST and SW. An internal diode is connected between VREG5 and VBST for charging. VBST(vs SW) max 6 V."+ "description": "Bootstrap supply for the high-side FET gate driver. Connect a 0.1 µF capacitor between VBST and SW. An internal diode is connected between VREG5 and VBST for charging. VBST(vs SW) max 6 V." }, { "number": "8",@@ -144,5 +144,8 @@ "docs/tps54427ddar-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }