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Contents

README

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TPS54383PWPR

Texas Instruments · DC-DC Converters · HTSSOP-14-EP

TPS54383PWPR from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PVDD1 power_in Power input to the Output 1 high-side MOSFET; bypass locally to GND with 10-μF or greater low-ESR ceramic capacitor.
2 BOOT1 input Gate driver supply input for Output 1; connect 22-nF to 82-nF capacitor from this pin to SW1, charged from BP through internal switch during converter OFF time.
3 SW1 output Switching output (source) for Output 1 PWM; a snubber is recommended to reduce ringing on this node.
4 GND power_in Ground pin for the device; connect directly to Thermal Pad.
5 EN1 input Active-low enable input for Output 1; disables above 1.55V, enables below 0.9V, driven to PVDD2 when floating; connect to GND for always-ON operation.
6 EN2 input Active-low enable input for Output 2; disables above 1.55V, enables below 0.9V, driven to PVDD2 when floating; connect to GND for always-ON operation.
7 FB1 input Feedback input for Output 1; internal error amplifier regulates this pin to 0.8-V reference through external resistor divider from output to ground.
8 FB2 input Feedback input for Output 2; internal error amplifier regulates this pin to 0.8-V reference through external resistor divider from output to ground.
9 ILIM2 input Current limit selection pin for Output 2 only; connection to BP sets 4.5A limit, floating sets 3.0A limit, GND sets 1.5A limit; includes internal 150-kΩ divider.
10 SEQ input Output startup sequencing control; connection to BP enables sequential mode (Output 1 slave), GND enables sequential mode (Output 2 slave), or floating for ratiometric startup; includes internal 150-kΩ divider.
11 BP power_out Regulated bootstrap supply output for gate drivers; internally generated 5.25-V supply; bypass to GND with 4.7-μF to 10-μF low-ESR ceramic capacitor.
12 SW2 output Switching output (source) for Output 2 PWM; a snubber is recommended to reduce ringing on this node.
13 BOOT2 input Gate driver supply input for Output 2; connect 22-nF to 82-nF capacitor from this pin to SW2, charged from BP through internal switch during converter OFF time.
14 PVDD2 power_in Power input to device control circuitry, EN1/EN2 pull-up driver, and Output 2 high-side MOSFET; bypass to GND with 10-μF or greater low-ESR ceramic capacitor; UVLO monitors this pin and enables device above 4.1V.
15 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-14-EP
Category Power Management (PMIC)
Pins 15

CAD (KiCad official)

  • Symbol: TPS54383PWPR
  • Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
  • 3D model files: tps54383pwpr-etched.step / tps54383pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54383pwpr.step / tps54383pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 39fce6f59b613d37, retrieved 2026-09-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF