component
TPS54373PWPR
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Texas Instruments DC-DC Converters, HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54373PWPR
Texas Instruments · DC-DC Converters · HTSSOP-20
TPS54373PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog ground and return for the compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin; connect the PowerPAD to AGND. |
| 2 | VSENSE | input | Error amplifier inverting input, connected to the output voltage through the compensation network/output divider; absolute maximum range is −0.3 V to 4 V. |
| 3 | COMP | output | Error amplifier output; the frequency compensation network is connected from COMP to VSENSE. |
| 4 | PWRGD | output | Open-drain power-good output that is high when VSENSE ≥ 90% Vref and low otherwise, and is also low when SS/ENA is low or internal shutdown is active; sink current is limited to 10 mA. |
| 5 | BOOT | power_out | Bootstrap output; a 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver. |
| 6 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum range is −0.6 V to 10 V. |
| 7 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum range is −0.6 V to 10 V. |
| 8 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum range is −0.6 V to 10 V. |
| 9 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum range is −0.6 V to 10 V. |
| 10 | PH | output | Phase output at the junction of the internal high-side and low-side power MOSFETs and the output inductor; absolute maximum range is −0.6 V to 10 V. |
| 11 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND. |
| 12 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND. |
| 13 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas and use a single-point connection to AGND. |
| 14 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3 V to 6 V; bypass to PGND close to the package with a low-ESR 10 µF ceramic capacitor. |
| 15 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3 V to 6 V; bypass to PGND close to the package with a low-ESR 10 µF ceramic capacitor. |
| 16 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating over 3 V to 6 V; bypass to PGND close to the package with a low-ESR 10 µF ceramic capacitor. |
| 17 | VBIAS | power_out | Internal bias regulator output supplying internal circuitry; bypass to AGND with a low-ESR 0.1 µF to 1.0 µF ceramic capacitor. |
| 18 | SS/ENA | bidirectional | Dual-function slow-start/enable pin: logic input to enable or disable operation (enable threshold 1.20 V typical) and capacitor input to set start-up time; sink current is limited to 10 mA. |
| 19 | SYNC | input | Synchronization input that locks to an external oscillator or selects between two internally set switching frequencies; when synchronizing, a resistor must be connected to RT. |
| 20 | RT | input | Frequency-setting resistor input; a resistor from RT to AGND sets the switching frequency, and when SYNC is used the RT value should set a frequency at or slightly below the external oscillator frequency. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS54373PWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps54373pwpr-etched.step/tps54373pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54373pwpr.step/tps54373pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
03b0dd9230ab25f0, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).