# TPS54362AQPWPRQ1

**Texas Instruments** · DC-DC Converters · HTSSOP-20

TPS54362AQPWPRQ1 from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NU | unconnected | Not-used pin; the pin table says 'Connect to ground', which conflicts with the pin-diagram note 'NU - Make no external connection'. |
| 2 | NU | unconnected | Not-used pin; the pin-diagram note says make no external connection. |
| 3 | SYNC | input | External synchronization clock input that overrides the internal oscillator, with an internal 62 kΩ (typical) pulldown to ground and a maximum switching frequency of 2.2 MHz. |
| 4 | LPM | input | Digital low-power mode control input with an internal 62 kΩ (typical) pulldown to ground; absolute maximum rating is 5.5 V. |
| 5 | EN | input | Enable input, internally pulled up, that requires an external pullup or pulldown; voltages below 0.7 V disable the regulator, and the absolute maximum rating is 60 V. |
| 6 | RT | output | External resistor to ground programs the internal oscillator frequency over 200 kHz to 2.2 MHz; absolute maximum rating is 5.5 V. |
| 7 | Rslew | output | External resistor to ground sets the slew rate of the internal switching FET; absolute maximum rating is 5.5 V. |
| 8 | RST | output | Active-low open-drain reset output that needs an external bias pullup through a resistor; absolute maximum rating is 5.5 V. |
| 9 | Cdly | bidirectional | External capacitor to ground programs the power-on-reset delay from 2.2 ms to 200 ms using 2.2 nF to 200 nF; absolute maximum rating is 8 V. |
| 10 | GND | power_in | Ground pin. |
| 11 | SS | bidirectional | External capacitor to ground programs the soft-start time; absolute maximum rating is 8 V. |
| 12 | OV_TH | input | Overvoltage sense input that monitors V(VReg) through the external resistor divider to set the overvoltage threshold; absolute maximum rating is 5.5 V. |
| 13 | RST_TH | input | Undervoltage and reset sense input that monitors V(VReg) through the external resistor divider to set the reset threshold; absolute maximum rating is 5.5 V. |
| 14 | VSENSE | input | Inverting input of the error amplifier for voltage-mode control; absolute maximum rating is 5.5 V. |
| 15 | COMP | bidirectional | Error-amplifier output for connecting external compensation components; absolute maximum rating is 7 V. |
| 16 | VReg | input | Internal low-side FET load to the output during start-up or to limit overshoot; the regulated output range is 0.9 V to 18 V and the absolute maximum rating is 20 V. |
| 17 | PH | output | Source of the internal switching FET; absolute maximum rating is 60 V, with transients down to -2 V for 30 ns and -1 V for 200 ns. |
| 18 | VIN | power_in | Unregulated input voltage with a 3.6 V to 48 V operating range and a 60 V absolute maximum; connect pin 18 and pin 19 together externally. |
| 19 | VIN | power_in | Unregulated input voltage with a 3.6 V to 48 V operating range and a 60 V absolute maximum; connect pin 18 and pin 19 together externally. |
| 20 | BOOT | output | External bootstrap capacitor connected to PH that drives the gate of the internal switching FET; absolute maximum rating is 65 V. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| EN input voltage | EN | -0.3 |  | 60 | V |  | 5 |
| VIN input voltage | VIN | -0.3 |  | 60 | V |  | 5 |
| VReg voltage | VReg | -0.3 |  | 20 | V |  | 5 |
| LPM voltage | LPM | -0.3 |  | 5.5 | V |  | 5 |
| OV_TH voltage | OV_TH | -0.3 |  | 5.5 | V |  | 5 |
| RST_TH voltage | RST_TH | -0.3 |  | 5.5 | V |  | 5 |
| SYNC voltage | SYNC | -0.3 |  | 5.5 | V |  | 5 |
| VSENSE voltage | VSENSE | -0.3 |  | 5.5 | V |  | 5 |
| BOOT voltage | BOOT | -0.3 |  | 65 | V |  | 5 |
| PH voltage | PH | -0.3 |  | 60 | V |  | 5 |
| PH voltage | PH | -2 |  | 60 | V | 30 ns | 5 |
| PH voltage | PH | -1 |  | 60 | V | 200 ns | 5 |
| PH voltage | PH | -0.85 |  | 60 | V | TJ = –40°C | 5 |
| PH voltage | PH | -0.5 |  | 60 | V | TJ = 125°C | 5 |
| RT voltage | RT | -0.3 |  | 5.5 | V |  | 5 |
| RST voltage | RST | -0.3 |  | 5.5 | V |  | 5 |
| Rslew voltage | Rslew | -0.3 |  | 5.5 | V |  | 5 |
| Cdly voltage | Cdly | -0.3 |  | 8 | V |  | 5 |
| SS voltage | SS | -0.3 |  | 8 | V |  | 5 |
| COMP voltage | COMP | -0.3 |  | 7 | V |  | 5 |
| Operating virtual junction temperature range | TJ | -40 |  | 150 | °C |  | 5 |
| Storage temperature range | Tstg | -55 |  | 165 | °C |  | 5 |
| Electrostatic discharge, HBM | V(ESD) | -2 |  | 2 | kV | Human-body model (HBM), per AEC Q100-002 | 5 |
| Electrostatic discharge, CDM | V(ESD) | -750 |  | 750 | V | Charged-device model (CDM), per AEC Q100-011 | 5 |
| Unregulated buck supply input voltage | VI | 3.6 |  | 48 | V | Unregulated buck supply input voltage (VIN, EN) | 6 |
| Regulator voltage range | V(VReg) | 0.9 |  | 18 | V |  | 6 |
| Input voltage at power up |  | 0.9 |  | 5.5 | V | Power up in low-power mode (LPM) or discontinuous mode (DCM) | 6 |
| Logic level inputs (RST, VSENSE, OV_TH, RST_TH, SYNC, RT) |  | 0 |  | 5.25 | V |  | 6 |
| Logic level inputs (SS, Cdly, COMP) |  | 0 |  | 6.5 | V |  | 6 |
| Operating junction temperature range | TJ | -40 |  | 150 | °C |  | 6 |
| Supply voltage on VIN pin, normal mode buck | V(VIN) | 3.6 |  | 48 | V | Normal mode–buck mode after initial start-up | 7 |
| High-voltage threshold on VIN pin (LPM disabled) | V(VIN) | 25 | 27 | 30 | V |  | 7 |
| Quiescent current, normal mode | I(q-Normal) |  | 5 | 10 | mA | Open-loop test – maximum duty cycle; V(VIN) = 7 V to 48 V | 7 |
| Quiescent current, low-power mode | I(q-LPM) |  | 65 | 75 | µA | I(VReg) < 1 mA, V(VIN) = 12 V, TA = 25°C | 7 |
| Shutdown current | I(SD) |  | 1 | 4 | µA | V(EN) = 0 V, device is OFF, TA = 25°C, V(VIN) = 12 V | 7 |
| Regulator output voltage | V(VReg) | 0.9 |  | 18 | V | V(VSENSE) = 0.8-V reference | 7 |
| Feedback voltage | V(VSENSE) | 0.788 | 0.8 | 0.812 | V | V(VReg) = 0.9 V to 18 V, V(VIN) = 7 V to 48 V | 7 |
| Switch current limit, cycle-by-cycle | I(CL) | 4 | 6 | 8 | A | V(VIN) = 12 V | 7 |
| Duty-cycle pulse duration (ON) | t(ON-Min) | 50 | 100 | 150 | ns |  | 7 |
| Duty-cycle pulse duration (OFF) | t(OFF-Min) | 100 | 200 | 250 | ns |  | 7 |
| Switch-mode frequency | f(SW) | 0.2 |  | 2.2 | MHz | Set using external resistor on RT pin | 7 |
| Accuracy of f(SW) |  | -10 |  | 10 | % |  | 7 |
| Leakage into EN pin, A-revision | Ilkg |  | 100 | 135 | µA | A-revision, V(EN) = 60 V | 7 |
| Leakage into EN pin, A-revision | Ilkg |  | 8 | 15 | µA | A-revision, V(EN) = 12 V | 7 |
| External capacitor charge current | IO | 1.4 | 2 | 2.6 | µA | V(EN) = high | 7 |
| Leakage into LPM pin | Ilkg |  | 65 | 95 | µA | V(LPM) = 5 V | 7 |
| Reset threshold for RST_TH pin | V(RST_TH) | 0.768 |  | 0.832 | V |  | 7 |
| Soft-start source current | I(SS) | 40 | 50 | 60 | µA |  | 7 |
| Leakage into SYNC pin | Ilkg |  | 65 | 95 | µA | SYNC = 5 V | 8 |
| Threshold for OV_TH pin | V(OV_TH) | 0.768 |  | 0.832 | V | Internal switch is OFF. | 8 |
| Input clock frequency for SYNC | f(SYNC) | 180 |  | 2200 | kHz | V(VIN) = 12 V, V(VReg) = 5 V, f(sw) < f(ext) < 2 × f(sw) | 8 |
| POR delay timer | td(POR) | 3.6 |  | 7 | ms | C2 = 4.7 nF | 8 |
| Reset filter time | td(RSTdly) | 10 | 20 | 35 | µs |  | 8 |
| Junction-to-ambient thermal resistance | RθJA |  | 43.8 |  | °C/W |  | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 21.4 |  | °C/W |  | 6 |
| Junction-to-board thermal resistance | RθJB |  | 18.5 |  | °C/W |  | 6 |
| Junction-to-top characterization parameter | ψJT |  | 0.5 |  | °C/W |  | 6 |
| Junction-to-board characterization parameter | ψJB |  | 18.3 |  | °C/W |  | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 1.2 |  | °C/W |  | 6 |

## CAD (KiCad official)

- Symbol: `TPS54362AQPWPRQ1`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tps54362aqpwprq1-etched.step` / `tps54362aqpwprq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54362aqpwprq1.step` / `tps54362aqpwprq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54362-q1) (44 pp, sha256 `81197f9afad901c9`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54362aqpwprq1-datasheet.pdf)