TPS54360BQDDAQ1 from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOT	output	A bootstrap capacitor is required between BOOT and SW, and if its voltage falls below the minimum needed for the high-side MOSFET the output switches off until it is refreshed.
2	VIN	power_in	Input supply voltage with a 4.5-V to 60-V operating range.
3	EN	input	Enable pin with an internal pullup current source that disables the device when pulled below 1.2 V and enables it when floating, and whose input undervoltage lockout is adjustable with two resistors.
4	RT/CLK	input	Sets the switching frequency with an external resistor to ground, or when pulled above the PLL upper threshold becomes a high-impedance synchronization clock input.
5	FB	input	Inverting input of the transconductance (gm) error amplifier.
6	COMP	output	Error amplifier output and input to the output switch PWM current comparator, where frequency compensation components connect.
7	GND	power_in	Ground pin that must be electrically connected to the exposed thermal pad on the printed circuit board for proper operation.
8	SW	output	Source of the internal high-side power MOSFET and the switching node of the converter.
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8-EP
Category	Power Management (PMIC)
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage	VIN	-0.3		65	V		4
EN pin voltage	EN	-0.3		8.4	V		4
FB pin voltage	FB	-0.3		3	V		4
COMP pin voltage	COMP	-0.3		3	V		4
RT/CLK pin voltage	RT/CLK	-0.3		3.6	V		4
BOOT-SW voltage	BOOT-SW	-0.3		8	V		4
SW voltage	SW	-0.6		65	V		4
SW voltage 10-ns transient	SW	-2		65	V	10-ns transient	4
Storage temperature range	Tstg	-65		150	°C		4
Operating junction temperature	TJ	-40		150	°C		4
Input voltage range	VI			60	V	VO + Vdo	4
Operating junction temperature	TJ	-40		150	°C		4
Operating input voltage		4.5		60	V		5
Internal undervoltage lockout threshold		4.1	4.3	4.48	V	Rising	5
Internal undervoltage lockout threshold hysteresis			325		mV		5
Shutdown supply current			2.25	4.5	μA	EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 60 V	5
Operating nonswitching supply current	IQ		146	175	μA	FB = 0.9 V, TA = 25°C	5
Enable threshold voltage		1.1	1.2	1.3	V	No voltage hysteresis, rising and falling	5
Input current at enable threshold +50 mV			-4.6		μA	Enable threshold +50 mV	5
Input current at enable threshold -50 mV		-0.58	-1.2	-1.8	μA	Enable threshold -50 mV	5
Hysteresis current		-2.2	-3.4	-4.5	μA		5
Enable to COMP active			346		µs	VIN = 12 V, TA = 25°C	5
Soft-start time			2.1		ms	fSW = 500 kHz, 10% to 90%	5
Soft-start time			0.42		ms	fSW = 2.5 MHz, 10% to 90%	5
Voltage reference	VFB	0.792	0.8	0.808	V		5
High-side MOSFET on-resistance	RDS(on)		92	190	mΩ	VIN = 12 V, BOOT-SW = 6 V	5
Error amplifier input current			50		nA		5
Error amplifier transconductance (gM)	gM		350		μS	-2 μA < ICOMP < 2 μA, VCOMP = 1 V	5
Error amplifier transconductance (gM) during soft-start	gM		77		μS	-2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V	5
Error amplifier DC gain			10000		V/V	VFB = 0.8 V	5
Minimum unity gain bandwidth		2500			kHz		5
Error amplifier source/sink		-30		30	μA	V(COMP) = 1 V, 100 mV overdrive	5
COMP to SW current transconductance			12		A/V		5
Current limit threshold		4.5	5.5	6.8	A	All VIN and temperatures, Open-loop	5
Current limit threshold		4.5	5.5	6.25	A	All temperatures, VIN = 12 V, Open-loop	5
Current limit threshold		5.2	5.5	5.85	A	VIN = 12 V, TA = 25°C, Open-loop	5
Current limit threshold delay			60		ns		5
Thermal shutdown			176		°C		5
Thermal shutdown hysteresis			12		°C		5
Switching frequency range using RT mode	fSW	100		2500	kHz		6
Switching frequency	fSW	450	500	550	kHz	RT = 200 kΩ	6
Switching frequency range using CLK mode	fSW	160		2300	kHz		6
Minimum CLK input pulse width		15			ns		6
RT/CLK high threshold		1.55		2	V		6
RT/CLK low threshold		0.5	1.2		V		6
RT/CLK falling edge to SW rising edge delay			55		ns	Measured at 500 kHz with RT resistor in series	6
PLL lock in time			78		μs	Measured at 500 kHz	6
Junction-to-ambient thermal resistance	θJA		42		°C/W	Standard board	4
Junction-to-top characterization parameter	ψJT		5.9		°C/W		4
Junction-to-board characterization parameter	ψJB		23.4		°C/W		4
Junction-to-case (top) thermal resistance	θJC(top)		45.8		°C/W		4
Junction-to-case (bottom) thermal resistance	θJC(bot)		3.6		°C/W		4
Junction-to-board thermal resistance	θJB		23.4		°C/W		4

CAD (KiCad official)

Symbol: TPS54360BQDDAQ1
Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
3D model: SOIC-8-EP (KiCad packages3D, STEP)
3D model files: tps54360bqddaq1-etched.step / tps54360bqddaq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54360bqddaq1.step / tps54360bqddaq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (50 pp, sha256 3465d697869310d0, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS54360BQDDAQ1

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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