TPS54350PWP

{
  "slug": "tps54350pwp",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power supply chip",
    "tps54350pwp",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tps54350pwp.kicad_sym",
    "tps54350pwp.kicad_mod",
    "tps54350pwp.glb",
    "tps54350pwp.step",
    "tps54350pwp.lbr",
    "docs/hero.png",
    "docs/tps54350pwp-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "tps54350pwp-hero.glb",
    "tps54350pwp-hero.overlay.json"
  ],
  "component": {
    "mpn": "TPS54350PWP",
    "manufacturer": "Texas Instruments",
    "package": "HTSSOP-16-EP",
    "pin_count": 17,
    "category": "Power Supply Chip",
    "subcategory": "DC-DC Converters",
    "datasheet": "https://www.ti.com/cn/lit/gpn/tps54350",
    "parts": {
      "symbol": "tps54350pwp.kicad_sym",
      "footprint": "tps54350pwp.kicad_mod",
      "model_3d": "tps54350pwp-hero.glb",
      "model_3d_plain": "tps54350pwp.glb",
      "model_3d_step": "tps54350pwp-etched.step",
      "model_3d_step_plain": "tps54350pwp.step",
      "lbr": "tps54350pwp.lbr"
    },
    "distributor_links": {
      "lcsc": "C1355443",
      "digikey": "296-15882-5-ND",
      "mouser": "595-TPS54350PWP"
    },
    "distributor_check": {
      "checked_at": "2026-10-08T22:03:29Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-15882-5-ND",
        "status": "found",
        "lifecycle": "Active"
      },
      "mouser": {
        "pn": "595-TPS54350PWP",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VIN",
        "type": "power_in",
        "description": "Input supply voltage, 4.5 V to 20 V, must be bypassed with a low ESR 10-µF ceramic capacitor."
      },
      {
        "number": "2",
        "name": "VIN",
        "type": "power_in",
        "description": "Input supply voltage, 4.5 V to 20 V, must be bypassed with a low ESR 10-µF ceramic capacitor."
      },
      {
        "number": "3",
        "name": "UVLO",
        "type": "input",
        "description": "Undervoltage lockout pin; an external resistive divider from VIN overrides the internal default VIN start and stop thresholds (never connect directly to VIN)."
      },
      {
        "number": "4",
        "name": "PWRGD",
        "type": "output",
        "description": "Open-drain power good output; low indicates the output is less than the desired output voltage."
      },
      {
        "number": "5",
        "name": "RT",
        "type": "input",
        "description": "Frequency setting pin; a resistor to AGND sets the switching frequency, while ground or floating selects an internally preselected frequency (250 kHz grounded, 500 kHz floating)."
      },
      {
        "number": "6",
        "name": "SYNC",
        "type": "bidirectional",
        "description": "Bidirectional synchronization I/O pin; an output when RT is floating or grounded, an input (falling edge) when an RT resistor is used."
      },
      {
        "number": "7",
        "name": "ENA",
        "type": "input",
        "description": "Enable pin; below 0.5 V the device stops switching, float the pin to enable."
      },
      {
        "number": "8",
        "name": "COMP",
        "type": "output",
        "description": "Error amplifier output; connect the frequency compensation network from COMP to VSENSE."
      },
      {
        "number": "9",
        "name": "VSENSE",
        "type": "input",
        "description": "Inverting input of the error amplifier."
      },
      {
        "number": "10",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground internally connected to sensitive analog circuitry; connect to PGND and PowerPAD."
      },
      {
        "number": "11",
        "name": "PGND",
        "type": "power_in",
        "description": "Power ground, the noisy internal ground carrying LSG driver return currents; connect to AGND and PowerPAD."
      },
      {
        "number": "12",
        "name": "VBIAS",
        "type": "power_out",
        "description": "Internal 8.0 V bias voltage output requiring a 1.0 µF ceramic bypass capacitor."
      },
      {
        "number": "13",
        "name": "LSG",
        "type": "output",
        "description": "Gate drive for the optional low side n-channel MOSFET; leave open if a Schottky diode from ground to PH is used instead."
      },
      {
        "number": "14",
        "name": "PH",
        "type": "power_out",
        "description": "Phase node, connect to the external L-C filter."
      },
      {
        "number": "15",
        "name": "PH",
        "type": "power_out",
        "description": "Phase node, connect to the external L-C filter."
      },
      {
        "number": "16",
        "name": "BOOT",
        "type": "passive",
        "description": "Bootstrap capacitor pin for the high side gate driver; connect a 0.1 µF ceramic capacitor from BOOT to PH."
      },
      {
        "number": "17",
        "name": "PowerPAD",
        "type": "power_in",
        "description": "Exposed thermal pad; PGND and AGND pins must be connected to it for proper operation."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The PowerPAD exposed thermal pad is not given a numbered pin in the datasheet pin table, so it is no; Pin 1 position is stated as the lower left corner of the device in the page 5 note, and pin numberin; The datasheet pages provided are 12 of 35; the pin table is on page 5 and the package dimensions (pa",
          "exposed pad 17 added from the footprint"
        ],
        "pages_sent": 12,
        "cost_usd": 0.0803,
        "at": "2026-10-08T22:02:50"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/tps54350",
        "pages": 35,
        "sha256": "34189e1da359cef8",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "tps54350pwp.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "7982746831c0bd23f4690608869ad67776faae5c762fb0376666126a3998921b",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tps54350pwp-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5.0,
          1.1
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "c0a90c1fad4bab59770ac7768f61204f4e570fceff8f0c4f05cf87ff70982fca",
        "checked": "2026-10-08",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}