# TPS54350PWP

**Texas Instruments** · DC-DC Converters · HTSSOP-16-EP

TPS54350PWP from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply voltage, 4.5 V to 20 V, must be bypassed with a low ESR 10-µF ceramic capacitor. |
| 2 | VIN | power_in | Input supply voltage, 4.5 V to 20 V, must be bypassed with a low ESR 10-µF ceramic capacitor. |
| 3 | UVLO | input | Undervoltage lockout pin; an external resistive divider from VIN overrides the internal default VIN start and stop thresholds (never connect directly to VIN). |
| 4 | PWRGD | output | Open-drain power good output; low indicates the output is less than the desired output voltage. |
| 5 | RT | input | Frequency setting pin; a resistor to AGND sets the switching frequency, while ground or floating selects an internally preselected frequency (250 kHz grounded, 500 kHz floating). |
| 6 | SYNC | bidirectional | Bidirectional synchronization I/O pin; an output when RT is floating or grounded, an input (falling edge) when an RT resistor is used. |
| 7 | ENA | input | Enable pin; below 0.5 V the device stops switching, float the pin to enable. |
| 8 | COMP | output | Error amplifier output; connect the frequency compensation network from COMP to VSENSE. |
| 9 | VSENSE | input | Inverting input of the error amplifier. |
| 10 | AGND | power_in | Analog ground internally connected to sensitive analog circuitry; connect to PGND and PowerPAD. |
| 11 | PGND | power_in | Power ground, the noisy internal ground carrying LSG driver return currents; connect to AGND and PowerPAD. |
| 12 | VBIAS | power_out | Internal 8.0 V bias voltage output requiring a 1.0 µF ceramic bypass capacitor. |
| 13 | LSG | output | Gate drive for the optional low side n-channel MOSFET; leave open if a Schottky diode from ground to PH is used instead. |
| 14 | PH | power_out | Phase node, connect to the external L-C filter. |
| 15 | PH | power_out | Phase node, connect to the external L-C filter. |
| 16 | BOOT | passive | Bootstrap capacitor pin for the high side gate driver; connect a 0.1 µF ceramic capacitor from BOOT to PH. |
| 17 | PowerPAD | power_in | Exposed thermal pad; PGND and AGND pins must be connected to it for proper operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Supply Chip |
| Pins | 17 |

## CAD (KiCad official)

- Symbol: `TPS54350PWP`
- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`
- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files: `tps54350pwp-etched.step` / `tps54350pwp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54350pwp.step` / `tps54350pwp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54350) (35 pp, sha256 `34189e1da359cef8`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54350pwp-datasheet.pdf)