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package.json tps54331d: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json tps54331d: specified limits as data (metadata.characteristics, 38 rows from the datasheet) · Ray 26d ago
README.md tps54331d: specified limits as data (metadata.characteristics, 38 rows from the datasheet) · Ray 26d ago
tps54331d-etched.fit.json tps54331d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps54331d-etched.glb tps54331d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
tps54331d-etched.step tps54331d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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TPS54331D

Texas Instruments · DC-DC Converters · SOIC-8

TPS54331D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT output Bootstrap supply output for high-side MOSFET gate drive; requires 0.1μF capacitor to PH pin; MOSFET forced off if voltage falls below 2.1V typical.
2 VIN power_in Main input power supply; operating range 3.5V to 28V, absolute maximum 30V.
3 EN input Active-high enable control; device disabled at 1.25V threshold; programmable UVLO via external resistor divider.
4 SS input Soft start capacitor connection; sets output ramp rate at 2μA charge current; recommended time range 1ms to 10ms with maximum 27nF capacitor.
5 VSENSE input Error amplifier inverting input for output voltage feedback; compares actual output to 0.8V internal reference; maximum pull current 10μA.
6 COMP output Error amplifier output and PWM comparator input; frequency compensation network elements connected here; maximum sink current 100μA.
7 GND power_in Ground reference terminal.
8 PH output High-side MOSFET source switch node output; maximum voltage 30V, minimum -0.6V, rated 9A peak pull current.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage, VIN pin VIN -0.3 30 V 4
Input voltage, EN pin EN -0.3 6 V 4
Input voltage, BOOT pin BOOT 38 V 4
Input voltage, VSENSE pin VSENSE -0.3 3 V 4
Input voltage, COMP pin COMP -0.3 3 V 4
Input voltage, SS pin SS -0.3 3 V 4
Output voltage, BOOT-PH BOOT-PH 8 V 4
Output voltage, PH pin PH -0.6 30 V 4
PH pin transient voltage PH -5 V 10 ns transient from GND to negative peak 4
Source current, EN pin EN 100 μA 4
Source current, BOOT pin BOOT 100 mA 4
Source current, VSENSE pin VSENSE 10 μA 4
Source current, PH pin PH 9 A 4
Sink current, VIN pin VIN 9 A 4
Sink current, COMP pin COMP 100 μA 4
Sink current, SS pin SS 200 μA 4
Operating junction temperature TJ -40 150 °C 4
Storage temperature range Tstg -65 150 °C 4
ESD, human body model (HBM) V(ESD) -2 2 kV ANSI/ESDA/JEDEC JS-001, all pins 4
ESD, charged device model (CDM) V(ESD) -500 500 V JEDEC JESD22-C101, all pins 4
Operating input voltage at VIN pin VIN 3.5 28 V 4
Operating junction temperature TJ -40 150 °C 4
Voltage reference VREF 0.772 0.8 0.828 V 5
Shutdown supply current IQ(SD) 1 4 μA EN = 0V, VIN = 12V, -40°C to 85°C 5
Operating non-switching supply current IQ 110 190 μA VSENSE = 0.85V 5
Enable threshold, rising and falling EN 1.25 1.35 V rising and falling 5
Current limit threshold ILIM 3.5 5.8 A VIN = 12V 5
Error amplifier source and sink current ICOMP -7 7 μA V(COMP) = 1V, 100mV overdrive 5
High-side MOSFET on-resistance RDS(on) 115 200 mΩ BOOT-PH = 3V, VIN = 3.5V 5
High-side MOSFET on-resistance RDS(on) 80 150 mΩ BOOT-PH = 6V, VIN = 12V 5
Switching frequency fSW 456 570 684 kHz VIN = 12V, 25°C 6
Minimum controllable on-time tON(min) 105 130 ns VIN = 12V, 25°C 6
Maximum controllable duty cycle DMAX 90 93 % BOOT-PH = 6V 6
Junction-to-ambient thermal resistance (D package) RθJA 116.3 °C/W 5
Junction-to-case (top) thermal resistance (D package) RθJC(top) 53.7 °C/W 5
Junction-to-board thermal resistance (D package) RθJB 57.1 °C/W 5
Junction-to-top characterization parameter (D package) ψJT 12.9 °C/W 5
Junction-to-board characterization parameter (D package) ψJB 56.5 °C/W 5

CAD (KiCad official)

  • Symbol: TPS54331D
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tps54331d-etched.step / tps54331d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54331d.step / tps54331d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 6ac89d4fddb009ba, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF