component
TPS54329EDDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
TPS54329EDDAR
Texas Instruments · DC-DC Converters · SOIC-8-EP
TPS54329EDDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBST | power_out | Supply for the high-side FET gate drive circuit that requires a 0.1µF capacitor between VBST and SW, with an internal diode connecting VREG5 to VBST. |
| 2 | VIN | power_in | Input voltage supply pin. |
| 3 | SW | output | Switch node connection between high-side NFET and low-side NFET. |
| 4 | GND | power_in | Ground pin and power ground return for switching circuit with sensitive SS and VFB returns connected to GND at a single point. |
| 5 | VFB | input | Converter feedback input connected to output voltage through feedback resistor divider. |
| 6 | VREG5 | power_out | 5.5 V power supply output requiring a typical 0.47µF capacitor connected to GND that is not active when EN is low. |
| 7 | EN | input | Enable input control that is active high and must be pulled up to enable the device. |
| 8 | SS | input | Soft-start control requiring an external capacitor connected to GND. |
| 9 | PowerPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
TPS54329EDDAR - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
tps54329eddar-etched.step/tps54329eddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54329eddar.step/tps54329eddar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
e254db6f7e01aa20, retrieved 2026-10-03, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS54329EDDAR
**Texas Instruments** · DC-DC Converters · SOIC-8-EP
TPS54329EDDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBST | power_out | Supply for the high-side FET gate drive circuit that requires a 0.1µF capacitor between VBST and SW, with an internal diode connecting VREG5 to VBST. |
| 2 | VIN | power_in | Input voltage supply pin. |
| 3 | SW | output | Switch node connection between high-side NFET and low-side NFET. |
| 4 | GND | power_in | Ground pin and power ground return for switching circuit with sensitive SS and VFB returns connected to GND at a single point. |
| 5 | VFB | input | Converter feedback input connected to output voltage through feedback resistor divider. |
| 6 | VREG5 | power_out | 5.5 V power supply output requiring a typical 0.47µF capacitor connected to GND that is not active when EN is low. |
| 7 | EN | input | Enable input control that is active high and must be pulled up to enable the device. |
| 8 | SS | input | Soft-start control requiring an external capacitor connected to GND. |
| 9 | PowerPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## CAD (KiCad official)
- Symbol: `TPS54329EDDAR`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`
- 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files: `tps54329eddar-etched.step` / `tps54329eddar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54329eddar.step` / `tps54329eddar.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54329e) (30 pp, sha256 `e254db6f7e01aa20`, retrieved 2026-10-03, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps54329eddar-datasheet.pdf)