component
TPS54329DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+45@@ -0,0 +1,45 @@+# TPS54329DDAR++**Texas Instruments** · DC-DC Converters · SOIC-8-EP++TPS54329DDAR from Texas Instruments, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBST | power_in | Bootstrap supply for high-side FET gate drive; connect 0.1µF capacitor between VBST and SW pins, with internal diode to VREG5. |+| 2 | VIN | power_in | Input voltage supply pin. |+| 3 | SW | output | Switch node connection between high-side NFET and low-side NFET. |+| 4 | GND | power_in | Power ground return for switching circuit; connect sensitive SS and VFB returns at a single point. |+| 5 | VFB | input | Converter feedback input; connect to output voltage with feedback resistor divider. |+| 6 | VREG5 | power_out | 5.5 V regulated power supply output; connect 0.47µF capacitor to GND (inactive when EN is low). |+| 7 | EN | input | Enable input control (active high); must be pulled up to enable the device. |+| 8 | SS | input | Soft-start control; connect external capacitor to GND for adjustable soft-start time. |+| 9 | Exposed Thermal Pad | power_in | Thermal pad for heat dissipation; must be soldered to PCB and connected to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8-EP |+| Category | Power Management (PMIC) |+| Pins | 9 |++## CAD (KiCad official)++- Symbol: `TPS54329DDAR`+- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm`+- 3D model: SOIC-8-EP (KiCad packages3D, STEP)+- 3D model files: `tps54329ddar-etched.step` / `tps54329ddar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54329ddar.step` / `tps54329ddar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54329) (30 pp, sha256 `4e69e9b93fb82133`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps54329ddar-datasheet.pdf)
page.jsonadded+150@@ -0,0 +1,150 @@+{+ "slug": "tps54329ddar",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "tps54329ddar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps54329ddar.kicad_sym",+ "tps54329ddar.kicad_mod",+ "tps54329ddar.glb",+ "tps54329ddar.step",+ "tps54329ddar.lbr",+ "docs/hero.png",+ "docs/tps54329ddar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "TPS54329DDAR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-8-EP",+ "pin_count": 9,+ "category": "Power Management (PMIC)",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps54329",+ "parts": {+ "symbol": "tps54329ddar.kicad_sym",+ "footprint": "tps54329ddar.kicad_mod",+ "model_3d": "tps54329ddar-etched.glb",+ "model_3d_plain": "tps54329ddar.glb",+ "model_3d_step": "tps54329ddar-etched.step",+ "model_3d_step_plain": "tps54329ddar.step",+ "lbr": "tps54329ddar.lbr"+ },+ "distributor_links": {+ "lcsc": "C37647"+ },+ "pins": [+ {+ "number": "1",+ "name": "VBST",+ "type": "power_in",+ "description": "Bootstrap supply for high-side FET gate drive; connect 0.1µF capacitor between VBST and SW pins, with internal diode to VREG5."+ },+ {+ "number": "2",+ "name": "VIN",+ "type": "power_in",+ "description": "Input voltage supply pin."+ },+ {+ "number": "3",+ "name": "SW",+ "type": "output",+ "description": "Switch node connection between high-side NFET and low-side NFET."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Power ground return for switching circuit; connect sensitive SS and VFB returns at a single point."+ },+ {+ "number": "5",+ "name": "VFB",+ "type": "input",+ "description": "Converter feedback input; connect to output voltage with feedback resistor divider."+ },+ {+ "number": "6",+ "name": "VREG5",+ "type": "power_out",+ "description": "5.5 V regulated power supply output; connect 0.47µF capacitor to GND (inactive when EN is low)."+ },+ {+ "number": "7",+ "name": "EN",+ "type": "input",+ "description": "Enable input control (active high); must be pulled up to enable the device."+ },+ {+ "number": "8",+ "name": "SS",+ "type": "input",+ "description": "Soft-start control; connect external capacitor to GND for adjustable soft-start time."+ },+ {+ "number": "9",+ "name": "Exposed Thermal Pad",+ "type": "power_in",+ "description": "Thermal pad for heat dissipation; must be soldered to PCB and connected to GND."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Thermal pad pin number (9) is inferred from package outline diagram on page 27. The PIN FUNCTIONS ta",+ "1/9 pins cited to the wrong page (name found elsewhere): ['9:Exposed Thermal Pad@p5']"+ ],+ "pages_sent": 30,+ "cost_usd": 0.2427,+ "at": "2026-09-22T19:29:08"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps54329",+ "pages": 30,+ "sha256": "4e69e9b93fb82133",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 9,+ "described": 9,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}