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TPS54325TPWPRQ1
Public Made by Adomby adom
Texas Instruments Pre-ordered Chips, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54325TPWPRQ1
Texas Instruments · Pre-ordered Chips · HTSSOP-14-EP
TPS54325TPWPRQ1 from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VO | input | Connect this pin to the output of the converter; used for on-time adjustment. |
| 2 | VFB | input | Converter feedback input; connect with a feedback resistor divider. |
| 3 | VREG5 | power_out | 5.5-V power supply output; connect a capacitor (typically 1μF) to GND. |
| 4 | SS | passive | Soft-start control; connect an external capacitor to GND. |
| 5 | GND | power_in | Signal ground pin. |
| 6 | PG | output | Open-drain power-good output. |
| 7 | EN | input | Enable control input (high level 2 V min, low level 0.4 V max, absolute maximum 20 V). |
| 8 | PGND1 | power_in | Ground return for low-side MOSFET and input of current comparators; connect PGND and GND strongly together near the IC. |
| 9 | PGND2 | power_in | Ground return for low-side MOSFET and input of current comparators; connect PGND and GND strongly together near the IC. |
| 10 | SW1 | passive | Switch node connection between the high-side NFET and low-side NFET, also an input to current comparators. |
| 11 | SW2 | passive | Switch node connection between the high-side NFET and low-side NFET, also an input to current comparators. |
| 12 | VBST | power_in | Supply input for high-side NFET gate driver (boost terminal); connect a capacitor to SW1 and SW2, with an internal PN diode from VREG5 to VBST. |
| 13 | VIN | power_in | Power input connected to high-side NFET drain; 2 V to 18 V operating range. |
| 14 | VCC | power_in | Supply input for the 5-V internal linear regulator for the control circuitry; 4.5 V to 18 V operating range. |
| 15 | PowerPAD | passive | Thermal pad on the back side of the package; must be soldered for proper dissipation and connected to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-14-EP |
| Category | Interface ICs |
| Pins | 15 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC Supply input voltage range | VCC | 4.5 | 18 | V | 4 | ||
| VIN Power input voltage range | VIN | 2 | 18 | V | 4 | ||
| Operating free-air temperature | TA | -40 | 105 | °C | 4 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| VREG5 output current range | IVREG5 | 0 | 10 | mA | 4 | ||
| EN input voltage range | EN | -0.1 | 18 | V | 4 | ||
| VBST input voltage range | VBST | -0.1 | 24 | V | 4 | ||
| VBST vs SW1, SW2 voltage | VBST-SW | -0.1 | 6 | V | 4 | ||
| SS, PG input voltage range | SS, PG | -0.1 | 6 | V | 4 | ||
| VO, VFB input voltage range | VO, VFB | -0.1 | 5.5 | V | 4 | ||
| SW1, SW2 voltage range | SW | -1.8 | 18 | V | 4 | ||
| SW1, SW2 voltage range (10-ns transient) | SW | -3 | 18 | V | 10-ns transient | 4 | |
| PGND1, PGND2 voltage range | PGND | -0.1 | 0.1 | V | 4 | ||
| VREG5 output voltage range | VREG5 | -0.1 | 6 | V | 4 | ||
| Input voltage VIN, VCC, EN | VI | -0.3 | 20 | V | VIN, VCC, EN | 4 | |
| Input voltage VBST | VBST | -0.3 | 26 | V | 4 | ||
| Input voltage VBST vs SW1, SW2 | VBST-SW | -0.3 | 6.5 | V | 4 | ||
| Input voltage VFB, VO, SS, PG | VI | -0.3 | 6.5 | V | VFB, VO, SS, PG | 4 | |
| Input voltage SW1, SW2 | SW | -2 | 20 | V | 4 | ||
| Input voltage SW1, SW2 (10-ns transient) | SW | -3 | 20 | V | 10-ns transient | 4 | |
| Output voltage VREG5 | VREG5 | -0.3 | 6.5 | V | 4 | ||
| Output voltage PGND1, PGND2 | PGND | -0.3 | 0.3 | V | 4 | ||
| Voltage from GND to POWERPAD | Vdiff | -0.2 | 0.2 | V | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | HBM per ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | CDM per JESD22-C101, all pins | 4 | |
| Operating nonswitching supply current | IVCC | 850 | 1300 | μA | VCC current, TA = 25°C, EN = 5 V, VFB = 0.8 V | 5 | |
| Shutdown supply current | ICCSDN | 10 | μA | VCC current, TA = 25°C, EN = 0 V | 5 | ||
| EN high-level input voltage | VENH | 2 | V | EN | 5 | ||
| EN low-level input voltage | VENL | 0.4 | V | EN | 5 | ||
| VFB threshold voltage | VFBTH | 757 | 765 | 775 | mV | TA = 25°C, VO = 1.05 V | 5 |
| VFB threshold voltage | VFBTH | 753 | 777 | mV | TA = 0°C to 105°C, VO = 1.05 V | 5 | |
| VFB threshold voltage | VFBTH | 750 | 780 | mV | TA = -40°C to 105°C, VO = 1.05 V | 5 | |
| VFB input current | IVFB | 0 | 0.1 | μA | VFB = 0.8 V, TA = 25°C | 5 | |
| VO discharge resistance | RDischg | 50 | 100 | Ω | EN = 0 V, VO = 0.5 V, TA = 25°C | 5 | |
| VREG5 output voltage | VVREG5 | 5.3 | 5.5 | 5.7 | V | TA = 25°C, 6.0 V < VCC < 18 V, 0 < IVREG5 < 5 mA | 5 |
| Line regulation | VLN5 | 20 | mV | 6.0 V < VCC < 18 V, IVREG5 = 5 mA | 5 | ||
| Load regulation | VLD5 | 100 | mV | 0 mA < IVREG5 < 5 mA | 5 | ||
| VREG5 output current | IREG5 | 70 | mA | VCC = 6 V, VREG5 = 4.0 V, TA = 25°C | 5 | ||
| High-side switch resistance | Rdsonh | 120 | mΩ | 25°C, VBST, SW1, SW2 = 5.5 V | 5 | ||
| Low-side switch resistance | Rdsonl | 70 | mΩ | 25°C | 5 | ||
| Current limit | Iocl | 3.5 | 4.1 | A | TA = 25°C to 105°C | 5 | |
| Current limit | Iocl | 3.25 | 3.5 | A | TA = -40°C | 5 | |
| Thermal shutdown threshold | tSDN | 150 | °C | Shutdown temperature | 5 | ||
| Thermal shutdown hysteresis | tSDN | 25 | °C | Hysteresis | 5 | ||
| On time | tON | 145 | ns | VIN = 12 V, VO = 1.05 V | 5 | ||
| Minimum off time | tOFF(MIN) | 260 | ns | TA = 25°C, VFB = 0.7 V | 5 | ||
| SS charge current | ISSC | 1.4 | 2 | 2.6 | μA | VSS = 0 V | 6 |
| SS discharge current | ISSD | 0.1 | 0.2 | mA | VSS = 0.5 V | 6 | |
| PG threshold (VFB rising, good) | VTHPG | 85 | 90 | 95 | % | VFB rising (good) | 6 |
| PG threshold (VFB falling, fault) | VTHPG | 85 | % | VFB falling (fault) | 6 | ||
| PG sink current | IPG | 2.5 | 5 | mA | PG = 0.5 V | 6 | |
| Output OVP trip threshold | VOVP | 115 | 120 | 125 | % | OVP detect | 6 |
| Output OVP prop delay | TOVPDEL | 5 | μs | 6 | |||
| Output UVP trip threshold | VUVP | 65 | 70 | 75 | % | UVP detect | 6 |
| Output UVP hysteresis | VUVP | 10 | % | Hysteresis | 6 | ||
| Output UVP delay | tUVPDEL | 0.25 | ms | 6 | |||
| UVLO wake-up threshold | VUVLO | 3.45 | 3.7 | 3.95 | V | Wake-up VREG5 voltage | 6 |
| UVLO hysteresis | VUVLO | 0.15 | 0.25 | 0.35 | V | Hysteresis VREG5 voltage | 6 |
| Junction-to-ambient thermal resistance | RθJA | 46.3 | °C/W | PWP 14 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 36.6 | °C/W | PWP 14 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 31.4 | °C/W | PWP 14 pins | 5 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 7.2 | °C/W | PWP 14 pins | 5 |
CAD (KiCad official)
- Symbol:
TPS54325TPWPRQ1 - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
- 3D model files:
tps54325tpwprq1-etched.step/tps54325tpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54325tpwprq1.step/tps54325tpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
96e46bdacba90fc5, retrieved 2026-11-02, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).