# TPS54325PWPR

**Texas Instruments** · DC-DC Converters · TSSOP-14-EP

TPS54325PWPR from Texas Instruments, in a TSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VO | input | Connect to output of converter; this terminal is used for on-time adjustment. |
| 2 | VFB | input | Converter feedback input; connect with feedback resistor divider (absolute max 6.5 V). |
| 3 | VREG5 | power_out | 5.5 V power supply output; a capacitor (typical 1µF) should be connected to GND. |
| 4 | SS | input | Soft-start control; an external capacitor should be connected to GND. |
| 5 | GND | power_in | Signal ground pin. |
| 6 | PG | output | Open drain power good output. |
| 7 | EN | input | Enable control input (absolute max 20 V). |
| 8 | PGND1 | power_in | Ground return for low-side MOSFET and input of current comparators; connect PGND and GND strongly together near the IC. |
| 9 | PGND2 | power_in | Ground return for low-side MOSFET and input of current comparators; connect PGND and GND strongly together near the IC. |
| 10 | SW1 | passive | Switch node connection between high-side NFET and low-side NFET, also an input to current comparators. |
| 11 | SW2 | passive | Switch node connection between high-side NFET and low-side NFET, also an input to current comparators. |
| 12 | VBST | passive | Supply input for high-side NFET gate driver (boost terminal); connect capacitor from this pin to SW1, SW2, with an internal PN diode between VREG5 and VBST. |
| 13 | VIN | power_in | Power input connected to high side NFET drain; 2.0 V to 18 V input range. |
| 14 | VCC | power_in | Supply input for 5 V internal linear regulator for the control circuitry; 4.5 V to 18 V range. |
| 15 | PowerPAD | passive | Thermal pad of the package; must be soldered to achieve appropriate dissipation and should be connected to PGND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14-EP |
| Category | Power Management (PMIC) |
| Pins | 15 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN, VCC, EN | -0.3 |  | 20 | V |  | 4 |
| Input voltage range | VBST | -0.3 |  | 26 | V |  | 4 |
| Input voltage range | VBST (vs SW1, SW2) | -0.3 |  | 6.5 | V |  | 4 |
| Input voltage range | SW1, SW2 | -2 |  | 20 | V |  | 4 |
| Input voltage range | SW1, SW2 | -3 |  | 20 | V | 10 ns transient | 4 |
| Output voltage range | VREG5 | -0.3 |  | 6.5 | V |  | 4 |
| Output voltage range | PGND1, PGND2 | -0.3 |  | 0.3 | V |  | 4 |
| Voltage from GND to POWERPAD | Vdiff | -0.2 |  | 0.2 | V |  | 4 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 4 |
| Storage temperature range | Tstg | -55 |  | 150 | °C |  | 4 |
| Supply input voltage range | VCC | 4.5 |  | 18 | V | over operating free-air temperature range | 5 |
| Power input voltage range | VIN | 2 |  | 18 | V | over operating free-air temperature range | 5 |
| Input voltage range | VBST | -0.1 |  | 24 | V | over operating free-air temperature range | 5 |
| Input voltage range | VBST (vs SW1, SW2) | -0.1 |  | 6 | V | over operating free-air temperature range | 5 |
| Input voltage range | EN | -0.1 |  | 18 | V | over operating free-air temperature range | 5 |
| Input voltage range | VO, VFB | -0.1 |  | 5.5 | V | over operating free-air temperature range | 5 |
| Input voltage range | SW1, SW2 | -1.8 |  | 18 | V | over operating free-air temperature range | 5 |
| Input voltage range | SW1, SW2 | -3 |  | 18 | V | 10 ns transient | 5 |
| Output voltage range | PGND1, PGND2 | -0.1 |  | 0.1 | V | over operating free-air temperature range | 5 |
| Output voltage range | VREG5 | -0.1 |  | 6 | V | over operating free-air temperature range | 5 |
| Output current range | IVREG5 | 0 |  | 10 | mA | over operating free-air temperature range | 5 |
| Operating free-air temperature | TA | -40 |  | 85 | °C |  | 5 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 5 |
| Operating non-switching supply current | IVCC |  | 850 | 1300 | μA | TA = 25°C, EN = 5 V, VFB = 0.8 V | 5 |
| Shutdown supply current | IVCCSDN |  |  | 10 | μA | TA = 25°C, EN = 0 V | 5 |
| EN high-level input voltage | VENH | 1.6 |  |  | V | EN | 5 |
| EN low-level input voltage | VENL |  |  | 0.4 | V | EN | 5 |
| VFB threshold voltage | VFBTH | 757 | 765 | 773 | mV | TA = 25°C, VO = 1.05 V | 5 |
| VFB threshold voltage | VFBTH | 753 |  | 777 | mV | TA = 0°C to 85°C, VO = 1.05 V; footnote (1) not production tested | 5 |
| VFB threshold voltage | VFBTH | 751 |  | 779 | mV | TA = -40°C to 85°C, VO = 1.05 V; footnote (1) not production tested | 5 |
| VFB input current | IVFB | -0.1 | 0 | 0.1 | μA | VFB = 0.8 V, TA = 25°C | 5 |
| VREG5 output voltage | VVREG5 | 5.3 | 5.5 | 5.7 | V | TA = 25°C, 6.0 V < VCC < 18 V, 0 < IVREG5 < 5 mA | 5 |
| Current limit | Iocl | 3.5 | 4.1 | 5.5 | A | TA = –40°C to 85°C; footnote (1) not production tested | 6 |
| Wake up VREG5 voltage (UVLO threshold) | VUVLO | 3.45 | 3.7 | 3.95 | V |  | 6 |
| Hysteresis VREG5 voltage (UVLO) |  | 0.15 | 0.25 | 0.35 | V |  | 6 |
| SS charge current | ISSC | 1.4 | 2 | 2.6 | μA | VSS = 0 V | 6 |
| PG threshold, VFB rising (good) | VTHPG | 85 | 90 | 95 | % | VFB rising (good) | 6 |
| Output OVP trip threshold | VOVP | 115 | 120 | 125 | % | OVP detect | 6 |
| Output UVP trip threshold | VUVP | 65 | 70 | 75 | % | UVP detect | 6 |
| Junction-to-ambient thermal resistance | RθJA |  | 55.6 |  | °C/W | PWP package; table header prints '12 PINS' | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 51.3 |  | °C/W | PWP package; table header prints '12 PINS' | 4 |
| Junction-to-board thermal resistance | RθJB |  | 26.4 |  | °C/W | PWP package; table header prints '12 PINS' | 4 |
| Junction-to-top characterization parameter | ψJT |  | 1.8 |  | °C/W | PWP package; table header prints '12 PINS' | 4 |
| Junction-to-board characterization parameter | ψJB |  | 20.6 |  | °C/W | PWP package; table header prints '12 PINS' | 4 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 4.3 |  | °C/W | PWP package; table header prints '12 PINS' | 4 |

## CAD (KiCad official)

- Symbol: `TPS54325PWPR`
- Footprint: `Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14-EP (KiCad packages3D, STEP)
- 3D model files: `tps54325pwpr-etched.step` / `tps54325pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54325pwpr.step` / `tps54325pwpr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54325) (31 pp, sha256 `5d0e4cda8e2a083e`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54325pwpr-datasheet.pdf)