component
TPS54318RTER
Public Made by Adomby adom
Texas Instruments DC-DC Converters, QFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS54318RTER
Texas Instruments · DC-DC Converters · QFN-16-EP(3x3)
TPS54318RTER from Texas Instruments, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Input supply voltage, 2.95 V to 6 V range. |
| 2 | VIN | power_in | Input supply voltage, 2.95 V to 6 V range. |
| 3 | GND | power_in | Power ground, should be electrically connected directly to the power pad under the device. |
| 4 | GND | power_in | Power ground, should be electrically connected directly to the power pad under the device. |
| 5 | AGND | power_in | Analog ground should be electrically connected to GND close to the device. |
| 6 | VSENSE | input | Inverting node of the transconductance error amplifier used for output voltage feedback regulation. |
| 7 | COMP | output | Error amplifier output and input to the output switch current comparator; connect frequency compensation components to this pin. |
| 8 | RT/CLK | bidirectional | Resistor timing or external clock input pin for switching frequency adjustment (200 kHz to 2000 kHz) or external clock synchronization (300 kHz to 2000 kHz). |
| 9 | SS | bidirectional | Soft-start pin; external capacitor connected to this pin sets the output voltage rise time. |
| 10 | PH | output | Source of the internal high-side power MOSFET and drain of the internal low-side synchronous rectifier MOSFET. |
| 11 | PH | output | Source of the internal high-side power MOSFET and drain of the internal low-side synchronous rectifier MOSFET. |
| 12 | PH | output | Source of the internal high-side power MOSFET and drain of the internal low-side synchronous rectifier MOSFET. |
| 13 | BOOT | input | Bootstrap capacitor connection (0.1 μF ceramic required between BOOT and PH); if voltage is below minimum required by BOOT UVLO, output is forced to switch off. |
| 14 | PWRGD | tri_state | Open drain output that asserts low when output voltage is low due to thermal shutdown, overcurrent, over/under-voltage, or EN shutdown condition. |
| 15 | EN | input | Enable pin with internal pull-up current source; pull below 1.2 V to disable, float to enable, adjustable UVLO with two external resistors. |
| 16 | VIN | power_in | Input supply voltage, 2.95 V to 6 V range. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-16-EP(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
TPS54318RTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
tps54318rter-etched.step/tps54318rter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54318rter.step/tps54318rter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (41 pp, sha256
1f9f20765ddc24aa, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).