component
TPS54315PWPR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers & Regulators, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+57@@ -0,0 +1,57 @@+# TPS54315PWPR++**Texas Instruments** · AC-DC Controllers & Regulators · HTSSOP-20-EP++TPS54315PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGND | power_in | Analog ground and return for the compensation network, output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin; the PowerPAD must be connected to AGND. |+| 2 | VSENSE | input | Error amplifier inverting input that must connect directly to the output voltage sense point. |+| 3 | NC | unconnected | No internal connection. |+| 4 | PWRGD | output | Open-drain powergood output that is high-impedance when VSENSE is at or above 90% of Vref and low otherwise, and is also low when SS/ENA is low or an internal shutdown is active; absolute maximum sink current is 10 mA. |+| 5 | BOOT | passive | Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating high-side FET driver supply. |+| 6 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together. |+| 7 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together. |+| 8 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together. |+| 9 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together. |+| 10 | PH | bidirectional | Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together. |+| 11 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 12 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 13 | PGND | power_in | Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns. |+| 14 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 15 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 16 | VIN | power_in | Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor. |+| 17 | VBIAS | power_out | Internal bias regulator output supplying internal circuitry, to be bypassed to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. |+| 18 | SS/ENA | bidirectional | Slow-start/enable input/output where a logic input enables or disables device operation and the capacitor input sets the start-up time; absolute maximum voltage is 7 V. |+| 19 | FSEL | input | Frequency select logic input that selects between two internally set switching frequencies. |+| 20 | RT | input | Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency fs. |+| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-20-EP |+| Category | Power Supply Chip |+| Pins | 21 |++## CAD (KiCad official)++- Symbol: `TPS54315PWPR`+- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`+- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)+- 3D model files: `tps54315pwpr-etched.step` / `tps54315pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54315pwpr.step` / `tps54315pwpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54315) (31 pp, sha256 `877a5f0bc56ab487`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tps54315pwpr-datasheet.pdf)
page.jsonadded+279@@ -0,0 +1,279 @@+{+ "slug": "tps54315pwpr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments AC-DC Controllers & Regulators, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "tps54315pwpr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tps54315pwpr.kicad_sym",+ "tps54315pwpr.kicad_mod",+ "tps54315pwpr.glb",+ "tps54315pwpr.step",+ "tps54315pwpr.lbr",+ "docs/hero.png",+ "docs/tps54315pwpr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tps54315pwpr-hero.glb",+ "tps54315pwpr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TPS54315PWPR",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-20-EP",+ "pin_count": 21,+ "category": "Power Supply Chip",+ "subcategory": "AC-DC Controllers & Regulators",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tps54315",+ "parts": {+ "symbol": "tps54315pwpr.kicad_sym",+ "footprint": "tps54315pwpr.kicad_mod",+ "model_3d": "tps54315pwpr-hero.glb",+ "model_3d_plain": "tps54315pwpr.glb",+ "model_3d_step": "tps54315pwpr-etched.step",+ "model_3d_step_plain": "tps54315pwpr.step",+ "lbr": "tps54315pwpr.lbr"+ },+ "distributor_links": {+ "lcsc": "C527517",+ "digikey": "296-34946-2-ND",+ "mouser": "595-TPS54315PWPR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T18:24:01Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-34946-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TPS54315PWPR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground and return for the compensation network, output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin; the PowerPAD must be connected to AGND."+ },+ {+ "number": "2",+ "name": "VSENSE",+ "type": "input",+ "description": "Error amplifier inverting input that must connect directly to the output voltage sense point."+ },+ {+ "number": "3",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "4",+ "name": "PWRGD",+ "type": "output",+ "description": "Open-drain powergood output that is high-impedance when VSENSE is at or above 90% of Vref and low otherwise, and is also low when SS/ENA is low or an internal shutdown is active; absolute maximum sink current is 10 mA."+ },+ {+ "number": "5",+ "name": "BOOT",+ "type": "passive",+ "description": "Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating high-side FET driver supply."+ },+ {+ "number": "6",+ "name": "PH",+ "type": "bidirectional",+ "description": "Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together."+ },+ {+ "number": "7",+ "name": "PH",+ "type": "bidirectional",+ "description": "Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together."+ },+ {+ "number": "8",+ "name": "PH",+ "type": "bidirectional",+ "description": "Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together."+ },+ {+ "number": "9",+ "name": "PH",+ "type": "bidirectional",+ "description": "Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together."+ },+ {+ "number": "10",+ "name": "PH",+ "type": "bidirectional",+ "description": "Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together."+ },+ {+ "number": "11",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "12",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "13",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns."+ },+ {+ "number": "14",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "15",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "16",+ "name": "VIN",+ "type": "power_in",+ "description": "Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor."+ },+ {+ "number": "17",+ "name": "VBIAS",+ "type": "power_out",+ "description": "Internal bias regulator output supplying internal circuitry, to be bypassed to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor."+ },+ {+ "number": "18",+ "name": "SS/ENA",+ "type": "bidirectional",+ "description": "Slow-start/enable input/output where a logic input enables or disables device operation and the capacitor input sets the start-up time; absolute maximum voltage is 7 V."+ },+ {+ "number": "19",+ "name": "FSEL",+ "type": "input",+ "description": "Frequency select logic input that selects between two internally set switching frequencies."+ },+ {+ "number": "20",+ "name": "RT",+ "type": "input",+ "description": "Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency fs."+ },+ {+ "number": "21",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed thermal pad (PowerPAD) is not given a pin number in the datasheet text, so no pin row wa; The pin table and top view list 20 pins, but the thermal information table header reads 'PWP (28 PIN; The pin list covers all datasheet package variants (TPS54311 through TPS54316 share the same PWP pin",+ "exposed pad 21 added from the footprint"+ ],+ "pages_sent": 11,+ "cost_usd": 0.086,+ "at": "2026-10-08T18:23:10"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tps54315",+ "pages": 31,+ "sha256": "877a5f0bc56ab487",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 21,+ "described": 21,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tps54315pwpr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e7d1561775dae9f300c585d0b7edc990c8bf18c2d5e0c2e1dc752e2486111137",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tps54315pwpr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.41,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "a1a597a06451f99777929a46e7c6c3d2d7a9bb1a820c85b7c186ec0c9f88a6db",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}