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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS54315PWPR

Texas Instruments · AC-DC Controllers & Regulators · HTSSOP-20-EP

TPS54315PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AGND	power_in	Analog ground and return for the compensation network, output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin; the PowerPAD must be connected to AGND.
2	VSENSE	input	Error amplifier inverting input that must connect directly to the output voltage sense point.
3	NC	unconnected	No internal connection.
4	PWRGD	output	Open-drain powergood output that is high-impedance when VSENSE is at or above 90% of Vref and low otherwise, and is also low when SS/ENA is low or an internal shutdown is active; absolute maximum sink current is 10 mA.
5	BOOT	passive	Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating high-side FET driver supply.
6	PH	bidirectional	Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together.
7	PH	bidirectional	Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together.
8	PH	bidirectional	Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together.
9	PH	bidirectional	Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together.
10	PH	bidirectional	Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum PH voltage is -0.6 V to 10 V, and PH pins 6 through 10 are to be tied together.
11	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns.
12	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns.
13	PGND	power_in	Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the input and output supply returns.
14	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
15	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
16	VIN	power_in	Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and to be bypassed to PGND close to the package with a 1-µF to 10-µF low-ESR ceramic capacitor.
17	VBIAS	power_out	Internal bias regulator output supplying internal circuitry, to be bypassed to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
18	SS/ENA	bidirectional	Slow-start/enable input/output where a logic input enables or disables device operation and the capacitor input sets the start-up time; absolute maximum voltage is 7 V.
19	FSEL	input	Frequency select logic input that selects between two internally set switching frequencies.
20	RT	input	Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency fs.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-20-EP
Category	Power Supply Chip
Pins	21

CAD (KiCad official)

Symbol: TPS54315PWPR
Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: tps54315pwpr-etched.step / tps54315pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54315pwpr.step / tps54315pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (31 pp, sha256 877a5f0bc56ab487, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF