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TPS54315MPWPREP

Public Made by Adom

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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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package.json tps54315mpwprep: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
page.json tps54315mpwprep: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 9d ago
README.md tps54315mpwprep: specified limits as data (metadata.characteristics, 44 rows from the datasheet) · Ray 10d ago
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TPS54315MPWPREP

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS54315MPWPREP from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground return for the compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin; make the PowerPAD connection to AGND.
2 VSENSE input Error amplifier inverting input that must connect directly to the output voltage sense point; power good trips when VSENSE is 10% below the reference.
3 NC unconnected No internal connection.
4 PWRGD output Open-drain power good output that is high impedance when VSENSE ≥ 90% Vref and otherwise low, and is also low when SS/ENA is low or internal shutdown is active.
5 BOOT input Bootstrap input; a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates the floating drive for the high-side FET driver.
6 PH bidirectional Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor.
7 PH bidirectional Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor.
8 PH bidirectional Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor.
9 PH bidirectional Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor.
10 PH bidirectional Phase input/output at the junction of the internal high- and low-side power MOSFETs and the output inductor.
11 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns and the negative terminals of the input and output capacitors.
12 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns and the negative terminals of the input and output capacitors.
13 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET; connect with large copper areas to the input and output supply returns and the negative terminals of the input and output capacitors.
14 VIN power_in Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 1-µF to 10-µF ceramic capacitor.
15 VIN power_in Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 1-µF to 10-µF ceramic capacitor.
16 VIN power_in Input supply for the power MOSFET switches and internal bias regulator; bypass to PGND close to the package with a high-quality, low-ESR 1-µF to 10-µF ceramic capacitor.
17 VBIAS power_out Internal bias regulator output supplying the internal circuitry; bypass to AGND with a high-quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.
18 SS/ENA bidirectional Dual-function slow-start/enable pin that provides the logic input to enable or disable operation and the capacitor input that externally sets the start-up time.
19 FSEL input Frequency select logic input that selects between two internally set switching frequencies.
20 RT input Frequency setting resistor input; connect a resistor from RT to AGND to set the switching frequency fs.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VI 3 6 V 4
Operating junction temperature TJ -55 125 °C 4
Input voltage range, VIN, SS/ENA, FSEL VI -0.3 7 V 4
Input voltage range, RT VI -0.3 6 V 4
Input voltage range, VSENSE VI -0.3 4 V 4
Input voltage range, BOOT VI -0.3 17 V 4
Output voltage range, VBIAS, PWRGD, COMP VO -0.3 7 V 4
Output voltage range, PH VO -0.6 10 V 4
Source current, COMP, VBIAS IO 6 mA 4
Source current, PH IO 6 A 4
Sink current, COMP IO 6 mA 4
Sink current, SS/ENA, PWRGD IO 10 mA 4
Voltage differential AGND to PGND -0.3 0.3 V 4
Operating virtual junction temperature range TJ -55 150 °C 4
Storage temperature Tstg -65 150 °C 4
Lead temperature 300 °C 1.6 mm (1/16 in) from case for 10 s 4
VIN input voltage range VI 3 6 V 5
Quiescent current 6.2 9.6 mA fs = 350 kHz, FSEL ≤ 0.8 V, RT open 5
Quiescent current 8.4 12.8 mA fs = 550 kHz, FSEL ≥ 2.5 V, Phase pin open, RT open 5
Shutdown current 1 1.4 mA Shutdown, SS/ENA = 0 V 5
UVLO start threshold voltage 2.95 3 V 5
UVLO stop threshold voltage 2.7 2.8 V 5
Output voltage, VBIAS 2.7 2.8 2.95 V IVBIAS = 0 5
Output voltage tolerance (TPS54315, 2.5 V) VO -3 3 % 3 ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −55°C ≤ TJ ≤ 125°C 5
Internally set free-running frequency 255 350 450 kHz FSEL ≤ 0.8 V, RT open 5
Internally set free-running frequency 400 550 700 kHz FSEL ≥ 2.5 V, RT open 5
Externally set free-running frequency 252 280 308 kHz RT = 180 kΩ (1% resistor to AGND) 5
Externally set free-running frequency 290 312 350 kHz RT = 160 kΩ (1% resistor to AGND) 5
Externally set free-running frequency 663 700 762 kHz RT = 68 kΩ (1% resistor to AGND) 5
Frequency range, FSEL 330 700 kHz 5
Error amplifier unity gain bandwidth 3 5 MHz 6
PWM comparator propagation delay time 70 85 ns PWM comparator input to PH pin, 10-mV overdrive (excluding dead time) 6
Enable threshold voltage, SS/ENA 0.82 1.2 1.4 V 6
Internal slow-start time 3.5 4.5 5.4 ms 6
Charge current, SS/ENA 2.5 5 8 µA SS/ENA = 0 V 6
Discharge current, SS/ENA 1.2 2.3 4 mA SS/ENA = 0.2 V, VI = 2.7 V 6
Output saturation voltage, PWRGD 0.18 0.3 V I(sink) = 2.5 mA 6
Current limit trip point 4 6.5 A VI = 3 V, output shorted 6
Thermal shutdown trip point 135 150 165 °C 6
Power MOSFET switches rDS(on) rDS(on) 59 88 mΩ VI = 6 V 6
Power MOSFET switches rDS(on) rDS(on) 85 136 mΩ VI = 3 V 6
Output voltage, nominal (TPS54315) VO 2.5 V TJ = 25°C, VIN = 5.0 V 5
Thermal impedance, junction-to-ambient, 20-pin PWP with solder 26 °C/W Test board per footnote (2), with solder 4
Thermal impedance, junction-to-ambient, 20-pin PWP without solder 57.5 °C/W Test board per footnote (2), without solder 4

CAD (KiCad official)

  • Symbol: TPS54315MPWPREP
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps54315mpwprep-etched.step / tps54315mpwprep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54315mpwprep.step / tps54315mpwprep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (22 pp, sha256 33d2837b152fe8e7, retrieved 2026-10-12, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF