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TPS54312PWPR

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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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package.json tps54312pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
page.json tps54312pwpr: etched from the flattened plain STEP (service-occt 1.6.0, from the plain STEP) · Ray 17d ago
README.md tps54312pwpr: specified limits as data (metadata.characteristics, 53 rows from the datasheet) · Ray 17d ago
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tps54312pwpr.step plain STEP: one free product with face colours (generated model was nested; tscircuit read it white) · Ray 17d ago

TPS54312PWPR

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS54312PWPR from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground and return for the compensation network, output divider, slow-start capacitor, VBIAS capacitor, RT resistor and FSEL pin, and must be connected to the PowerPAD.
2 VSENSE input Error amplifier inverting input that must connect directly to the output voltage sense point.
3 NC unconnected No internal connection.
4 PWRGD output Open-drain powergood output that is high impedance when VSENSE is at or above 90% of Vref and low otherwise, and is low when SS/ENA is low or an internal shutdown is active.
5 BOOT input Bootstrap input that requires a 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH to generate the floating high-side FET drive.
6 PH bidirectional Phase node at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum voltage is -0.6 V to 10 V.
7 PH bidirectional Phase node at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum voltage is -0.6 V to 10 V.
8 PH bidirectional Phase node at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum voltage is -0.6 V to 10 V.
9 PH bidirectional Phase node at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum voltage is -0.6 V to 10 V.
10 PH bidirectional Phase node at the junction of the internal high- and low-side power MOSFETs and the output inductor; absolute maximum voltage is -0.6 V to 10 V.
11 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the supply returns and capacitor negative terminals.
12 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the supply returns and capacitor negative terminals.
13 PGND power_in Power ground and high-current return for the low-side driver and power MOSFET, to be connected with large copper areas to the supply returns and capacitor negative terminals.
14 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package.
15 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package.
16 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, operating from 3 V to 6 V and bypassed to PGND with a low-ESR 1-µF to 10-µF ceramic capacitor placed close to the package.
17 VBIAS power_out Internal bias regulator output that supplies internal circuitry and must be bypassed to AGND with a high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
18 SS/ENA bidirectional Dual-function slow-start and enable pin that provides a logic input to enable or disable operation and a capacitor input to set the start-up time.
19 FSEL input Frequency select logic input that selects between two internally set switching frequencies.
20 RT input Frequency-setting resistor input; connect a resistor from RT to AGND to set the switching frequency fs.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VIN, SS/ENA, SYNC VI -0.3 7 V 4
Input voltage RT VI -0.3 6 V 4
Input voltage VSENSE VI -0.3 4 V 4
Input voltage BOOT VI -0.3 17 V 4
Output voltage VBIAS, PWRGD, COMP VO -0.3 7 V 4
Output voltage PH VO -0.6 10 V 4
Source current COMP, VBIAS IO 6 mA 4
Sink current PH IS 6 A 4
Sink current COMP IS 6 mA 4
Sink current SS/ENA, PWRGD IS 10 mA 4
Voltage differential AGND to PGND -0.3 0.3 V 4
Operating virtual junction temperature TJ TJ -40 125 °C 4
Storage temperature Tstg -65 150 °C 4
Input voltage range VI 3 6 V 4
Operating junction temperature TJ -40 125 °C 4
Input voltage range VIN VIN 3 6 V 5
Quiescent current I(Q), fs = 350 kHz I(Q) 6.2 9.6 mA fs = 350 kHz, FSEL ≤ 0.8 V, RT open 5
Quiescent current I(Q), fs = 550 kHz I(Q) 8.4 12.8 mA fs = 550 kHz, FSEL ≤ 2.5 V, RT open, Phase pin open 5
Shutdown quiescent current I(Q) 1 1.4 mA Shutdown, SS/ENA = 0 V 5
UVLO start threshold voltage 2.95 3 V 5
UVLO stop threshold voltage 2.7 2.8 V 5
UVLO hysteresis voltage 0.14 0.16 V 5
VBIAS output voltage VBIAS 2.7 2.8 2.9 V I(VBIAS) = 0 5
Output voltage TPS54312 (1.2 V), TJ = 25°C VO 1.2 V TJ = 25°C, VIN = 5 V 5
Output voltage tolerance TPS54312 VO -2.5 2.5 % 3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40°C ≤ TJ ≤ 125°C 5
Minimum controllable on time 200 ns 5
Maximum duty cycle 90 % 5
Error amplifier unity gain bandwidth 3 5 MHz 6
PWM comparator propagation delay 70 85 ns 10-mV overdrive (excluding dead time) 6
Enable threshold voltage SS/ENA 0.82 1.2 1.4 V 6
Internal slow-start time TPS54312 3.5 4.5 5.4 ms 6
Charge current SS/ENA 3 5 8 µA SS/ENA = 0 V 6
Discharge current SS/ENA 1.5 2.3 4 mA SS/ENA = 0.2 V, VI = 1.5 V 6
Output saturation voltage PWRGD 0.18 0.3 V I(sink) = 2.5 mA 6
Current limit at VI = 3 V, output shorted 6.5 A VI = 3 V, output shorted 6
Current limit at VI = 6 V, output shorted 4.5 7.5 A VI = 6 V, output shorted 6
Thermal shutdown trip point 135 150 165 °C 6
Power MOSFET rDS(on) at VI = 6 V rDS(on) 59 88 mΩ VI = 6 V 6
Power MOSFET rDS(on) at IO = 3 A, VI = 3 V rDS(on) 85 136 mΩ IO = 3 A, VI = 3 V 6
Line regulation 0.21 %/V IL = 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C 5
Load regulation 0.21 %/A IL = 0 A to 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C 5
Enable hysteresis voltage SS/ENA 0.03 V 6
Falling edge deglitch SS/ENA 2.5 µs 6
Powergood threshold voltage 90 %Vref VSENSE falling 6
Powergood hysteresis voltage 3 %Vref 6
Powergood falling edge deglitch 35 µs 6
Leakage current PWRGD 1 µA VI = 5.5 V 6
VBIAS output current 100 µA Static resistive loads only 5
Current limit leading edge blanking time 100 ns 6
Current limit total response time 200 ns 6
Thermal shutdown hysteresis 10 °C 6
Junction-to-ambient thermal resistance RθJA RθJA 26 °C/W PWP package with solder on PowerPAD; test board per footnote (1) 4
Junction-to-ambient thermal resistance without solder on PowerPAD RθJA 57.5 °C/W Without solder on PowerPAD; test board per footnote (1) 4

CAD (KiCad official)

  • Symbol: TPS54312PWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps54312pwpr-etched.step / tps54312pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54312pwpr.step / tps54312pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 877a5f0bc56ab487, retrieved 2026-10-10, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF