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TPS54310PWPR

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Texas Instruments DC-DC Converters, TSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps54310pwprfactory-2.0.0extractor-text

Verified TPS54310PWPR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 21 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS54310PWPR · TSSOP-20-EP · 21 pins
  • ✓copper: 21 copper pads, none touching another net
  • ✓datasheet: all 21 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C9379, digikey 296-26989-2-ND, mouser 595-TPS54310PWPR
  • ✓family: TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-cypp6_wf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 21 pins = 21 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 21 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps54310pwpr.kicad_sym✓ tps54310pwpr.kicad_mod✓ tps54310pwpr.step
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TPS54310PWPR

Texas Instruments · DC-DC Converters · TSSOP-20-EP

TPS54310PWPR from Texas Instruments, in a TSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground return for the compensation network, output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin, and the PowerPAD must be connected to AGND.
2 VSENSE input Error amplifier inverting input.
3 COMP output Error amplifier output, with the compensation network connected from COMP to VSENSE.
4 PWRGD output Open-drain power good output that is high when VSENSE is at or above 90% of Vref and low otherwise, and is low when SS/ENA is low or internal shutdown is active.
5 BOOT input Bootstrap input, where a 0.022-µF to 0.1-µF low-ESR capacitor from BOOT to PH generates the floating high-side FET driver supply.
6 PH bidirectional Phase input/output that forms the junction of the internal high- and low-side power MOSFETs and the output inductor.
7 PH bidirectional Phase input/output that forms the junction of the internal high- and low-side power MOSFETs and the output inductor.
8 PH bidirectional Phase input/output that forms the junction of the internal high- and low-side power MOSFETs and the output inductor.
9 PH bidirectional Phase input/output that forms the junction of the internal high- and low-side power MOSFETs and the output inductor.
10 PH bidirectional Phase input/output that forms the junction of the internal high- and low-side power MOSFETs and the output inductor.
11 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET, and should connect to large copper areas at the supply returns.
12 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET, and should connect to large copper areas at the supply returns.
13 PGND power_in Power ground that is the high-current return for the low-side driver and power MOSFET, and should connect to large copper areas at the supply returns.
14 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, which should be bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor close to the package.
15 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, which should be bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor close to the package.
16 VIN power_in Input supply for the power MOSFET switches and internal bias regulator, which should be bypassed to PGND with a 1-µF to 10-µF low-ESR ceramic capacitor close to the package.
17 VBIAS power_out Internal bias regulator output that supplies regulated voltage to internal circuitry and should be bypassed to AGND with a 0.1-µF to 1.0-µF low-ESR ceramic capacitor.
18 SS/ENA bidirectional Slow-start/enable input/output that provides a logic input to enable or disable device operation and a capacitor input to externally set the start-up time.
19 SYNC input Synchronization input that synchronizes to an external oscillator or selects between two internally set switching frequencies, and requires a resistor on the RT pin when synchronized externally.
20 RT input Frequency setting resistor input, where a resistor from RT to AGND sets the switching frequency fs.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20-EP
Category Power Management (PMIC)
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VI 3 6 V 4
Operating junction temperature TJ -40 125 °C 4
Input voltage VIN, SS/ENA, SYNC VI -0.3 7 V 4
Input voltage RT VI -0.3 6 V 4
Input voltage VSENSE VI -0.3 4 V 4
Input voltage BOOT VI -0.3 17 V 4
Output voltage VBIAS, PWRGD, COMP VO -0.3 7 V 4
Output voltage PH VO -0.6 10 V 4
Sink current COMP, VBIAS IO 6 mA 4
Sink current PH IO 6 A 4
Sink current COMP IO 6 mA 4
Sink current SS/ENA, PWRGD IO 10 mA 4
Voltage differential AGND to PGND -0.3 0.3 V 4
Operating virtual junction temperature TJ -40 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance (with solder) RθJA 26 °C/W 4
Junction-to-ambient thermal resistance (without solder on PowerPad) RθJA 57.5 °C/W 4
Quiescent current fs=350 kHz IQ 6.2 9.6 mA fs = 350 kHz, SYNC = 0.8 V, RT open 5
Quiescent current fs=550 kHz IQ 8.4 12.8 mA fs = 550 kHz, SYNC ≥ 2.5 V, RT open, phase pin open 5
Shutdown current IQ 1 1.4 mA Shutdown, SS/ENA = 0 V 5
Start threshold voltage, UVLO 2.95 3 V 5
Stop threshold voltage, UVLO 2.7 2.8 V 5
Hysteresis voltage, UVLO 0.14 0.16 V 5
Output voltage VBIAS VO 2.7 2.8 2.9 V I(VBIAS) = 0 5
Vref accuracy Vref 0.882 0.891 0.9 V 5
Line regulation 0.07 %/V IL = 1.5 A, fs = 350 kHz, TJ = 85°C 5
Load regulation 0.03 %/A IL = 0 A to 3 A, fs = 350 kHz, TJ = 85°C 5
Internally set free-running frequency fs 280 350 420 kHz SYNC ≤ 0.8 V, RT open 5
Internally set free-running frequency fs 440 550 660 kHz SYNC ≥ 2.5 V, RT open 5
Externally set free-running frequency fs 252 280 308 kHz RT = 180 kΩ (1% resistor to AGND) 5
Externally set free-running frequency fs 460 500 540 kHz RT = 100 kΩ (1% resistor to AGND) 5
Externally set free-running frequency fs 663 700 762 kHz RT = 68 kΩ (1% resistor to AGND) 5
Frequency range, SYNC fs 330 700 kHz 5
Maximum duty cycle 90 % 6
Minimum controllable on time 200 ns 6
Error amplifier open loop voltage gain 90 110 dB 1 kΩ COMP to AGND 6
Error amplifier unity gain bandwidth 3 5 MHz Parallel 10 kΩ, 160 pF COMP to AGND 6
Error amplifier common-mode input voltage range 0 V Powered by internal LDO 6
Input bias current, VSENSE IIB 60 250 nA VSENSE = Vref 6
Output voltage slew rate (symmetric), COMP VO 1 1.4 V/µs 6
PWM comparator propagation delay time 70 85 ns 10 mV overdrive 6
Enable threshold voltage, SS/ENA 0.82 1.2 1.4 V 6
Internal slow-start time 2.6 3.35 4.1 ms 6
Charge current, SS/ENA 3 5 8 µA SS/ENA = 0 V 6
Discharge current, SS/ENA 1.5 2.3 4 mA SS/ENA = 0.2 V, VI = 2.7 V 6
Power good threshold voltage 90 %Vref VSENSE falling 6
Power good hysteresis voltage 3 %Vref 6
Power good falling edge deglitch 35 µs 6
Output saturation voltage, PWRGD 0.18 0.3 V I(sink) = 2.5 mA 6
Current limit trip point 4 6.5 A VI = 3 V, output shorted 6
Current limit trip point 4.5 7.5 A VI = 6 V, output shorted 6
Current limit leading edge blanking time 100 ns 6
Current limit total response time 200 ns 6
Thermal shutdown trip point 135 150 165 °C 6
Thermal shutdown hysteresis 10 °C 6
Power MOSFET on-resistance rDS(on) 59 88 mΩ IO = 3 A, VI = 6 V 6
Power MOSFET on-resistance rDS(on) 85 136 mΩ IO = 3 A, VI = 3 V 6

CAD (KiCad official)

  • Symbol: TPS54310PWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: TSSOP-20-EP (KiCad packages3D, STEP)
  • 3D model files: tps54310pwpr-etched.step / tps54310pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54310pwpr.step / tps54310pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 6363abf1dbdb591c, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF