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TPS54262QPWPRQ1

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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS54262QPWPRQ1

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

TPS54262QPWPRQ1 from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Not internally connected; the datasheet instructs that this pin be connected to ground.
2 NC unconnected Not internally connected; the datasheet instructs that this pin be connected to ground.
3 SYNC input External synchronization clock input that overrides the internal oscillator, with an internal 62 kΩ (typical) pulldown to ground; connect to GND if not used.
4 LPM input Digital low-power mode control input with an internal 62 kΩ (typical) pulldown to ground.
5 EN input Enable pin, internally pulled up, that must be externally pulled up or down to enable or disable the device.
6 RT output External resistor to ground programs the internal oscillator frequency.
7 Rslew output External resistor to ground controls the slew rate of the internal switching FET.
8 RST output Active-low, open-drain reset output connected to an external bias voltage through a resistor, asserted high after the device starts regulating.
9 Cdly output External capacitor to ground programs the power-on reset delay.
10 GND power_in Ground pin that must be electrically connected to the exposed pad on the PCB for proper thermal performance.
11 SS output External capacitor to ground programs the soft-start time.
12 OV_TH input Sense input for overvoltage detection, with an external resistor network between VReg and ground setting the overvoltage threshold.
13 RST_TH input Sense input for undervoltage detection on the regulated output, with an external resistor network between VReg and ground setting the reset and undervoltage threshold.
14 VSENSE input Inverting node of the error amplifier for voltage-mode control.
15 COMP output Error amplifier output that connects to external compensation components.
16 VReg input Connects to the internal low-side FET that loads the output during start-up or limits overshoot.
17 PH output Source of the internal switching FET.
18 VIN power_in Unregulated input voltage; pin 18 and pin 19 must be connected externally.
19 VIN power_in Unregulated input voltage; pin 18 and pin 19 must be connected externally.
20 BOOT output External bootstrap capacitor connected to PH drives the gate of the internal switching FET.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Supply Chip
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage, EN -0.3 60 V 4
Input voltage, VIN -0.3 60 V 4
Input voltage, VReg -0.3 20 V 4
Input voltage, LPM -0.3 5.5 V 4
Input voltage, OV_TH -0.3 5.5 V 4
Input voltage, RST_TH -0.3 5.5 V 4
Input voltage, SYNC -0.3 5.5 V 4
Input voltage, VSENSE -0.3 5.5 V 4
Input voltage, BOOT -0.3 65 V 4
DC voltage (pin label unclear in text, see review) -0.3 60 V 4
PH DC voltage -0.85 V TJ = -40°C 4
PH DC voltage -0.5 V TJ = 125°C 4
Output voltage, 30-ns transient pulse -2 V 30-ns transient pulse 4
Output voltage, 200-ns transient pulse -1 V 200-ns transient pulse 4
Input voltage, RT -0.3 5.5 V 4
Input voltage, RST -0.3 5.5 V 4
Input voltage, Cdly -0.3 8 V 4
Input voltage, SS -0.3 8 V 4
Input voltage, COMP -0.3 7 V 4
Operating virtual junction temperature TJ -40 150 °C 4
Storage temperature Tstg -55 165 °C 4
Unregulated buck supply input voltage (VIN, EN) VI 3.6 48 V 4
Regulated output VReg VReg 0.9 18 V In continuous conduction mode (CCM) 4
Regulated output VReg VReg 0.9 5.5 V Power up in low-power mode (LPM) or discontinuous conduction mode (DCM) 4
Bootstrap capacitor (BOOT) 3.6 56 V 4
Switched outputs (PH) 3.6 48 V 4
Logic levels (RST, VSENSE, OV_TH, RST_TH, Rslew, SYNC, RT) 0 5.25 V 4
Logic levels (SS, Cdly, COMP) 0 6.5 V 4
Operating ambient temperature TA -40 125 °C 4
VIN supply, normal mode after initial start-up VIN 3.6 48 V 6
High voltage threshold (VIN) 29 31 34 V LPM disabled 6
Quiescent current, normal mode Iq-Normal 5 10 mA Open loop test – maximum duty cycle, VIN = 7 V to 48 V 6
Quiescent current, low-power mode Iq-LPM 50 70 µA Load < 1 mA, VIN = 12 V, TA = 25°C 6
Quiescent current, low-power mode Iq-LPM 75 µA Load < 1 mA, VIN = 12 V, –40 < TJ < 150°C 6
Shutdown current ISD 1 4 µA EN = 0 V, device is off, TA = 25°C, VIN = 12 V 6
Regulator output VReg 0.9 18 V VSENSE = 0.8 Vref 6
Feedback voltage VSENSE 0.788 0.8 0.812 V VReg = 0.9 V to 18 V (open loop) 6
Switch current limit, cycle by cycle ICL 2.5 3.2 4.1 A VIN = 12 V 6
Duty cycle pulse width (minimum on-time) tON-Min 50 100 150 ns Bench CHAR only 6
Minimum off-time tOFF-Min 100 200 250 ns Bench CHAR only 6
Switching frequency fsw 0.2 2.2 MHz Set using external resistor on RT pin 6
Internal oscillator frequency tolerance fsw -10 10 % 6
Internal reference voltage tolerance tolVref -1.5 1.5 % 12
Soft-start source current ISS 40 50 60 µA 7
Leakage current into EN terminal Ilkg 100 135 µA EN = 60 V 7
External capacitor charge current (Cdly) IO 1.4 2 2.6 µA EN = high 7
Leakage current into LPM terminal Ilkg 65 95 µA LPM = 5 V 7
POR delay timer trdly 3.6 7 ms/nF Based on Cdly capacitor 7
Reset threshold voltage for VReg VReg_RST 0.768 0.832 V Check RST output 7
Filter time, delay before RST asserted low tnRSTdly 10 20 35 µs 7
Overvoltage threshold voltage for VReg VReg_OV 0.768 0.832 V Internal switch is turned off during overvoltage 7
Leakage current SYNC Ilkg 65 95 µA SYNC = 5 V 7
External input clock frequency (SYNC) fext 180 2200 kHz VIN = 12 V, VReg = 5 V 7
Junction-to-ambient thermal resistance RθJA 36.2 °C/W 5
Junction-to-case (top) thermal resistance RθJC(top) 20.9 °C/W 5
Junction-to-board thermal resistance RθJB 17.9 °C/W 5
Junction-to-top characterization parameter ψJT 0.5 °C/W 5
Junction-to-board characterization parameter ψJB 17.7 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.4 °C/W 5

CAD (KiCad official)

  • Symbol: TPS54262QPWPRQ1
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps54262qpwprq1-etched.step / tps54262qpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54262qpwprq1.step / tps54262qpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (51 pp, sha256 b8063859464ccfa2, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF