component
TPS54260DGQ
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HVSSOP-10-EP-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS54260DGQ
Texas Instruments · DC-DC Converters · HVSSOP-10-EP-0.5mm
TPS54260DGQ from Texas Instruments, in a HVSSOP-10-EP-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap capacitor is required between BOOT and PH; if the capacitor voltage falls below the minimum required by the output device, the output is forced off until the capacitor is refreshed. |
| 2 | VIN | power_in | Input supply voltage, 3.5 V to 60 V. |
| 3 | EN | input | Enable pin with internal pull-up current source; pull below 1.2 V to disable, float to enable, or adjust the input undervoltage lockout with two resistors. |
| 4 | SS/TR | input | Slow-start and tracking pin where an external capacitor sets the output rise time, and its voltage overrides the internal reference so it can be used for tracking and sequencing. |
| 5 | RT/CLK | input | Resistor timing and external clock pin; a resistor to ground sets the switching frequency, and pulling above the PLL upper threshold turns it into a high-impedance synchronization clock input. |
| 6 | PWRGD | output | Open-drain power-good output that asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or EN shutdown. |
| 7 | VSENSE | input | Inverting node of the transconductance (gm) error amplifier. |
| 8 | COMP | output | Error amplifier output and input to the output switch current comparator; frequency compensation components connect to this pin. |
| 9 | GND | power_in | Ground. |
| 10 | PH | output | Source of the internal high-side power MOSFET. |
| 11 | Thermal Pad | power_in | Exposed thermal pad that must be electrically connected to the GND pin on the printed circuit board for proper operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-10-EP-0.5mm |
| Category | Power Management ICs |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN | VIN | -0.3 | 65 | V | 5 | ||
| Input voltage EN | EN | -0.3 | 5 | V | 5 | ||
| Input voltage VSENSE | VSENSE | -0.3 | 3 | V | 5 | ||
| Input voltage COMP | COMP | -0.3 | 3 | V | 5 | ||
| Input voltage PWRGD | PWRGD | -0.3 | 6 | V | 5 | ||
| Input voltage SS/TR | SS/TR | -0.3 | 3 | V | 5 | ||
| Input voltage RT/CLK | RT/CLK | -0.3 | 3.6 | V | 5 | ||
| Output voltage BOOT-PH | BOOT-PH | -0.3 | 8 | V | 5 | ||
| Output voltage PH | PH | -0.6 | 65 | V | 5 | ||
| Output voltage PH, 10-ns transient | PH | -5 | 65 | V | 10-ns transient | 5 | |
| Voltage difference PAD to GND | -200 | 200 | mV | 5 | |||
| Source current EN | EN | 100 | μA | 5 | |||
| Source current BOOT | BOOT | 100 | mA | 5 | |||
| Source current VSENSE | VSENSE | 10 | μA | 5 | |||
| Source current RT/CLK | RT/CLK | 100 | μA | 5 | |||
| Sink current COMP | COMP | 100 | μA | 5 | |||
| Sink current PWRGD | PWRGD | 10 | mA | 5 | |||
| Sink current SS/TR | SS/TR | 200 | μA | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 5 | |
| ESD CDM | V(ESD) | -500 | 500 | V | Charged-device model (CDM), per JEDEC specification JESD22-C101 | 5 | |
| Input supply voltage | VI | 3.5 | 60 | V | 5 | ||
| Output current | IO | 2.5 | A | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 62.5 | °C/W | DGQ, standard board | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 83 | °C/W | DGQ | 6 | ||
| Junction-to-board thermal resistance | RθJB | 28 | °C/W | DGQ | 6 | ||
| Junction-to-top characterization parameter | ψJT | 1.7 | °C/W | DGQ | 6 | ||
| Junction-to-board characterization parameter | ψJB | 20.1 | °C/W | DGQ | 6 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 21 | °C/W | DGQ | 6 | ||
| Operating input voltage | VIN | 3.5 | 60 | V | 6 | ||
| Shutdown supply current | 1.3 | 4 | μA | EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V | 6 | ||
| Operating: nonswitching supply current | 138 | 200 | μA | VSENSE = 0.83 V, VIN = 12 V, 25°C | 6 | ||
| Enable threshold voltage | 1.15 | 1.25 | 1.36 | V | No voltage hysteresis, rising and falling | 6 | |
| Voltage reference | VREF | 0.792 | 0.8 | 0.808 | V | TJ = 25°C | 6 |
| Voltage reference over temperature | VREF | 0.784 | 0.8 | 0.816 | V | 6 | |
| High-side MOSFET on-resistance | 300 | mΩ | VIN = 3.5 V, BOOT-PH = 3 V | 6 | |||
| High-side MOSFET on-resistance | 200 | 410 | mΩ | VIN = 12 V, BOOT-PH = 6 V | 6 | ||
| Current limit threshold | 3.5 | 6.1 | A | VIN = 12 V, TJ = 25°C | 6 | ||
| Switching frequency range using RT mode | fSW | 100 | 2500 | kHz | 7 | ||
| Switching frequency | fSW | 450 | 581 | 720 | kHz | RT = 200 kΩ | 7 |
| Switching frequency range using CLK mode | fSW | 300 | 2200 | kHz | 7 | ||
| RT/CLK high threshold | 1.9 | 2.2 | V | 7 | |||
| RT/CLK low threshold | 0.5 | 0.7 | V | 7 | |||
| Minimum VIN for defined PWRGD output | 0.95 | 1.5 | V | V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA | 7 | ||
| Internal undervoltage lockout threshold | 2.5 | V | No voltage hysteresis, rising and falling | 6 | |||
| Error amplifier transconductance | gM | 310 | μS | -2 μA < ICOMP < 2 μA, VCOMP = 1 V | 6 | ||
| Thermal shutdown | 182 | °C | 6 |
CAD (KiCad official)
- Symbol:
TPS54260DGQ - Footprint:
Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm - 3D model: HVSSOP-10-EP-0.5mm (KiCad packages3D, STEP)
- 3D model files:
tps54260dgq-etched.step/tps54260dgq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54260dgq.step/tps54260dgq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (61 pp, sha256
3dd6e95a60a876fa, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS54260DGQ
**Texas Instruments** · DC-DC Converters · HVSSOP-10-EP-0.5mm
TPS54260DGQ from Texas Instruments, in a HVSSOP-10-EP-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | passive | Bootstrap capacitor is required between BOOT and PH; if the capacitor voltage falls below the minimum required by the output device, the output is forced off until the capacitor is refreshed. |
| 2 | VIN | power_in | Input supply voltage, 3.5 V to 60 V. |
| 3 | EN | input | Enable pin with internal pull-up current source; pull below 1.2 V to disable, float to enable, or adjust the input undervoltage lockout with two resistors. |
| 4 | SS/TR | input | Slow-start and tracking pin where an external capacitor sets the output rise time, and its voltage overrides the internal reference so it can be used for tracking and sequencing. |
| 5 | RT/CLK | input | Resistor timing and external clock pin; a resistor to ground sets the switching frequency, and pulling above the PLL upper threshold turns it into a high-impedance synchronization clock input. |
| 6 | PWRGD | output | Open-drain power-good output that asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage or EN shutdown. |
| 7 | VSENSE | input | Inverting node of the transconductance (gm) error amplifier. |
| 8 | COMP | output | Error amplifier output and input to the output switch current comparator; frequency compensation components connect to this pin. |
| 9 | GND | power_in | Ground. |
| 10 | PH | output | Source of the internal high-side power MOSFET. |
| 11 | Thermal Pad | power_in | Exposed thermal pad that must be electrically connected to the GND pin on the printed circuit board for proper operation. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-10-EP-0.5mm |
| Category | Power Management ICs |
| Pins | 11 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage VIN | VIN | -0.3 | | 65 | V | | 5 |
| Input voltage EN | EN | -0.3 | | 5 | V | | 5 |
| Input voltage VSENSE | VSENSE | -0.3 | | 3 | V | | 5 |
| Input voltage COMP | COMP | -0.3 | | 3 | V | | 5 |
| Input voltage PWRGD | PWRGD | -0.3 | | 6 | V | | 5 |
| Input voltage SS/TR | SS/TR | -0.3 | | 3 | V | | 5 |
| Input voltage RT/CLK | RT/CLK | -0.3 | | 3.6 | V | | 5 |
| Output voltage BOOT-PH | BOOT-PH | -0.3 | | 8 | V | | 5 |
| Output voltage PH | PH | -0.6 | | 65 | V | | 5 |
| Output voltage PH, 10-ns transient | PH | -5 | | 65 | V | 10-ns transient | 5 |
| Voltage difference PAD to GND | | -200 | | 200 | mV | | 5 |
| Source current EN | EN | | | 100 | μA | | 5 |
| Source current BOOT | BOOT | | | 100 | mA | | 5 |
| Source current VSENSE | VSENSE | | | 10 | μA | | 5 |
| Source current RT/CLK | RT/CLK | | | 100 | μA | | 5 |
| Sink current COMP | COMP | | | 100 | μA | | 5 |
| Sink current PWRGD | PWRGD | | | 10 | mA | | 5 |
| Sink current SS/TR | SS/TR | | | 200 | μA | | 5 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 5 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 5 |
| ESD HBM | V(ESD) | -2000 | | 2000 | V | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 | 5 |
| ESD CDM | V(ESD) | -500 | | 500 | V | Charged-device model (CDM), per JEDEC specification JESD22-C101 | 5 |
| Input supply voltage | VI | 3.5 | | 60 | V | | 5 |
| Output current | IO | | | 2.5 | A | | 5 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 62.5 | | °C/W | DGQ, standard board | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 83 | | °C/W | DGQ | 6 |
| Junction-to-board thermal resistance | RθJB | | 28 | | °C/W | DGQ | 6 |
| Junction-to-top characterization parameter | ψJT | | 1.7 | | °C/W | DGQ | 6 |
| Junction-to-board characterization parameter | ψJB | | 20.1 | | °C/W | DGQ | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | | 21 | | °C/W | DGQ | 6 |
| Operating input voltage | VIN | 3.5 | | 60 | V | | 6 |
| Shutdown supply current | | | 1.3 | 4 | μA | EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V | 6 |
| Operating: nonswitching supply current | | | 138 | 200 | μA | VSENSE = 0.83 V, VIN = 12 V, 25°C | 6 |
| Enable threshold voltage | | 1.15 | 1.25 | 1.36 | V | No voltage hysteresis, rising and falling | 6 |
| Voltage reference | VREF | 0.792 | 0.8 | 0.808 | V | TJ = 25°C | 6 |
| Voltage reference over temperature | VREF | 0.784 | 0.8 | 0.816 | V | | 6 |
| High-side MOSFET on-resistance | | | | 300 | mΩ | VIN = 3.5 V, BOOT-PH = 3 V | 6 |
| High-side MOSFET on-resistance | | | 200 | 410 | mΩ | VIN = 12 V, BOOT-PH = 6 V | 6 |
| Current limit threshold | | 3.5 | | 6.1 | A | VIN = 12 V, TJ = 25°C | 6 |
| Switching frequency range using RT mode | fSW | 100 | | 2500 | kHz | | 7 |
| Switching frequency | fSW | 450 | 581 | 720 | kHz | RT = 200 kΩ | 7 |
| Switching frequency range using CLK mode | fSW | 300 | | 2200 | kHz | | 7 |
| RT/CLK high threshold | | | 1.9 | 2.2 | V | | 7 |
| RT/CLK low threshold | | 0.5 | 0.7 | | V | | 7 |
| Minimum VIN for defined PWRGD output | | | 0.95 | 1.5 | V | V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA | 7 |
| Internal undervoltage lockout threshold | | | 2.5 | | V | No voltage hysteresis, rising and falling | 6 |
| Error amplifier transconductance | gM | | 310 | | μS | -2 μA < ICOMP < 2 μA, VCOMP = 1 V | 6 |
| Thermal shutdown | | | 182 | | °C | | 6 |
## CAD (KiCad official)
- Symbol: `TPS54260DGQ`
- Footprint: `Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm`
- 3D model: HVSSOP-10-EP-0.5mm (KiCad packages3D, STEP)
- 3D model files: `tps54260dgq-etched.step` / `tps54260dgq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54260dgq.step` / `tps54260dgq.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps54260) (61 pp, sha256 `3dd6e95a60a876fa`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps54260dgq-datasheet.pdf)