# TPS54240QDGQRQ1

**Texas Instruments** · DC-DC Converters · HVSSOP-10-EP-0.5mm

TPS54240QDGQRQ1 from Texas Instruments, in a HVSSOP-10-EP-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | Bootstrap capacitor connects between BOOT and PH; if its voltage falls below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. |
| 2 | VIN | power_in | Input supply voltage, 3.5 V to 42 V. |
| 3 | EN | input | Enable pin with internal pullup current source; pull below 1.2 V to disable and float to enable, and adjust the input undervoltage lockout with two resistors. |
| 4 | SS/TR | input | Slow-start and tracking pin; an external capacitor sets the output rise time, and because this voltage overrides the internal reference it can be used for tracking and sequencing. |
| 5 | RT/CLK | input | Resistor timing and external clock pin; an internal amplifier holds a fixed voltage with a resistor to ground, and above the PLL upper threshold the pin becomes a high-impedance synchronization clock input. |
| 6 | PWRGD | output | Open-drain output that asserts low if the output voltage is low due to thermal shutdown, dropout, overvoltage or EN shutdown. |
| 7 | VSENSE | input | Inverting node of the transconductance (gm) error amplifier. |
| 8 | COMP | output | Error amplifier output and input to the output switch current comparator; frequency compensation components connect to this pin. |
| 9 | GND | power_in | Ground. |
| 10 | PH | input | Source of the internal high-side power MOSFET. |
| 11 | Thermal Pad | power_in | GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-10-EP-0.5mm |
| Category | Power Management (PMIC) |
| Pins | 11 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating ambient temperature | TA | -40 |  | 125 | °C | Operating ambient temperature | 2 |
| Operating input voltage | VIN | 3.5 |  | 42 | V |  | 3 |
| Input voltage VIN absolute maximum | VIN | -0.3 |  | 47 | V |  | 2 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 2 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 2 |
| Human-body model ESD rating | HBM |  |  | 2 | kV | AEC-Q100 Classification Level H2 | 2 |
| Charged-device model ESD rating | CDM |  |  | 1000 | V | AEC-Q100 Classification Level C6 | 2 |
| Thermal resistance junction-to-ambient (standard board) | θJA |  | 62.5 |  | °C/W | Standard board | 3 |
| Thermal resistance junction-to-ambient (custom board) | θJA |  | 57 |  | °C/W | Custom board | 3 |
| Junction-to-case (top) thermal resistance | θJCtop |  | 83 |  | °C/W |  | 3 |
| Junction-to-board thermal resistance | θJB |  | 28 |  | °C/W |  | 3 |
| Junction-to-top characterization parameter | ψJT |  | 1.7 |  | °C/W |  | 3 |
| Junction-to-board characterization parameter | ψJB |  | 20.1 |  | °C/W |  | 3 |
| Junction-to-case (bottom) thermal resistance | θJCbot |  | 21 |  | °C/W |  | 3 |
| Operating input voltage | VIN | 3.5 |  | 42 | V | TJ = -40°C to 150°C | 3 |
| Internal undervoltage lockout threshold | VUVLO |  |  | 2.5 | V | No voltage hysteresis, rising and falling | 3 |
| Shutdown supply current | IQ(SD) |  | 1.3 | 4 | μA | EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V | 3 |
| Operating nonswitching supply current | IQ |  | 138 | 200 | μA | VSENSE = 0.83 V, VIN = 12 V, 25°C | 3 |
| Enable threshold voltage | VEN | 1.15 | 1.25 | 1.36 | V | No voltage hysteresis, rising and falling, 25°C | 3 |
| Enable threshold input current +50 mV | II(EN) |  |  | -3.8 | μA | Enable threshold 50 mV | 3 |
| Enable threshold input current -50 mV | II(EN) |  |  | -0.9 | μA | Enable threshold -50 mV | 3 |
| Enable hysteresis current | Ihys |  |  | -2.9 | μA |  | 3 |
| Voltage reference at TJ = 25°C | VREF | 0.792 | 0.8 | 0.808 | V | TJ = 25°C | 3 |
| Voltage reference over temperature | VREF | 0.784 | 0.8 | 0.816 | V |  | 3 |
| High-side MOSFET on-resistance | rDS(on) |  | 300 |  | mΩ | VIN = 3.5 V, BOOT-PH = 3 V | 3 |
| High-side MOSFET on-resistance | rDS(on) |  | 200 | 410 | mΩ | VIN = 12 V, BOOT-PH = 6 V | 3 |
| Error amplifier input current | II(EA) |  |  | 50 | nA |  | 3 |
| Error amplifier transconductance (gm) | gm |  | 310 |  | μMhos | -2 μA < ICOMP < 2 μA, VCOMP = 1 V | 3 |
| Error amplifier transconductance (gm) during slow start | gm |  | 70 |  | μMhos | -2 μA < ICOMP < 2 μA, VCOMP = 1 V, VVSENSE = 0.4 V | 3 |
| Error amplifier dc gain | AVEA |  | 10000 |  | V/V | VVSENSE = 0.8 V | 3 |
| Error amplifier bandwidth | BW |  | 2700 |  | kHz |  | 3 |
| Error amplifier source/sink current | IEA | -27 |  | 27 | μA | V(COMP) = 1 V, 100 mV overdrive | 3 |
| COMP to switch current transconductance | gCOMP |  | 10.5 |  | A/V |  | 3 |
| Current limit threshold | ILIM | 3.5 |  | 6.1 | A | VIN = 12 V, TJ = 25°C | 4 |
| Thermal shutdown | TSD |  |  | 182 | °C |  | 4 |
| Switching-frequency range using RT | fSW | 100 |  | 2500 | kHz | RT mode | 4 |
| Switching frequency | fSW | 450 | 581 | 720 | kHz | RT = 200 kΩ | 4 |
| Switching-frequency range using CLK | fSW | 300 |  | 2200 | kHz | CLK mode | 4 |
| Minimum CLK input pulse duration | tCLK | 40 |  |  | ns |  | 4 |
| RT/CLK high threshold | VRT/CLK(H) | 1.9 | 2.2 |  | V |  | 4 |
| RT/CLK low threshold | VRT/CLK(L) |  | 0.7 | 0.5 | V |  | 4 |
| RT/CLK falling edge to PH rising edge delay | tdelay |  |  | 60 | ns | Measured at 500 kHz with RT resistor in series | 4 |
| PLL lock-in time | tlock |  |  | 100 | μs | Measured at 500 kHz | 4 |
| SS/TR charge current | ISS |  | 2 |  | μA | VSS/TR = 0.4 V | 4 |
| SS/TR-to-VSENSE matching | VSS-VSENSE |  | 45 |  | mV | VSS/TR = 0.4 V | 4 |
| SS/TR-to-reference crossover | VSS/TR |  | 1.15 |  | V | 98% nominal | 4 |
| SS/TR discharge current (overload) | ISS(dis) |  | 382 |  | μA | VSENSE = 0 V, V(SS/TR) = 0.4 V | 4 |
| SS/TR discharge voltage | VSS(dis) |  |  | 54 | mV | VSENSE = 0 V | 4 |
| PWRGD VSENSE falling threshold | VVSENSE |  | 92 |  | % | VSENSE falling | 4 |
| PWRGD VSENSE rising threshold | VVSENSE |  | 94 |  | % | VSENSE rising | 4 |
| PWRGD VSENSE rising overvoltage threshold | VVSENSE |  | 109 |  | % | VSENSE rising | 4 |
| PWRGD VSENSE falling overvoltage threshold | VVSENSE |  | 107 |  | % | VSENSE falling | 4 |
| PWRGD hysteresis | VHYS |  | 2 |  | % | VSENSE falling | 4 |
| PWRGD output-high leakage | IOH(PWRGD) |  |  | 10 | nA | VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C | 4 |
| PWRGD on-resistance | RDS(on) |  |  | 50 | Ω | I(PWRGD) = 3 mA, VSENSE < 0.79 V | 4 |
| Minimum VIN for defined PWRGD output | VIN(min) |  | 0.95 | 1.5 | V | V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA | 4 |

## CAD (KiCad official)

- Symbol: `TPS54240QDGQRQ1`
- Footprint: `Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm`
- 3D model: HVSSOP-10-EP-0.5mm (KiCad packages3D, STEP)
- 3D model files: `tps54240qdgqrq1-etched.step` / `tps54240qdgqrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54240qdgqrq1.step` / `tps54240qdgqrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps54240-q1.pdf) (54 pp, sha256 `66fc4fe1fb264e65`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54240qdgqrq1-datasheet.pdf)