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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206

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tps54225pwp-etched.glb	tps54225pwp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
tps54225pwp-etched.step	tps54225pwp: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
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TPS54225PWP

Texas Instruments · DC-DC Converters · HTSSOP-14-EP

TPS54225PWP from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VO	input	Connect to the output of the converter; this pin is used for on-time adjustment.
2	VFB	input	Converter feedback input; connect with feedback resistor divider (threshold typically 765 mV at 25°C).
3	VREG5	power_out	5.5 V power supply output; a capacitor (typical 1 µF) should be connected to GND.
4	SS	passive	Soft-start control; an external capacitor should be connected to GND.
5	GND	power_in	Signal ground pin.
6	PG	output	Open drain power good output.
7	EN	input	Enable control input (high level above 2 V, low level below 0.4 V; absolute max 20 V).
8	PGND1	power_in	Ground return for low-side MOSFET and input of current comparators; connect PGND1, PGND2 and GND strongly together near the IC.
9	PGND2	power_in	Ground return for low-side MOSFET and input of current comparators; connect PGND1, PGND2 and GND strongly together near the IC.
10	SW2	passive	Switch node between high-side and low-side NFET and input to current comparators.
11	SW1	passive	Switch node between high-side and low-side NFET and input to current comparators.
12	VBST	passive	Supply input for high-side NFET gate driver (boost terminal); connect capacitor from this pin to SW1, SW2 terminals, with an internal PN diode from VREG5 to VBST.
13	VIN	power_in	Power input connected to high side NFET drain; recommended range 2 V to 18 V.
14	VCC	power_in	Supply input for the 5 V internal linear regulator for control circuitry; recommended range 4.5 V to 18 V.
15	PowerPAD	passive	Thermal pad on package back side; must be soldered for adequate dissipation and should be connected to PGND.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-14-EP
Category	Power Management (PMIC)
Pins	15

CAD (KiCad official)

Symbol: TPS54225PWP
Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
3D model files: tps54225pwp-etched.step / tps54225pwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54225pwp.step / tps54225pwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (29 pp, sha256 3c3ac317d4ab1b65, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF