# TPS54202DDCR

**Texas Instruments** · DC-DC Converters · SOT-23-6

The TPS54202 is a 4.5 V to 28 V input, 2 A synchronous buck converter. It integrates both switching FETs, internal loop compensation and a 5 ms soft start to cut the part count, and the SOT-23 package gives it high power density in a small footprint. Eco-mode keeps light-load efficiency high, frequency spread spectrum reduces EMI, and cycle-by-cycle current limiting on the high-side FET, a low-side freewheeling limit and hiccup mode protect it in overload. (From TI's datasheet, SLVSD26A.)

Pinout and pin descriptions are extracted from the manufacturer datasheet by ds2sf.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin. Source terminal of the low-side power NFET as well as the ground terminal for controller circuit. Connect sensitive VFB return to this GND at a single point. |
| 2 | SW | output | Switch node connection between the high-side NFET and low-side NFET. Connect the external inductor here. Rated -0.3 V to 30 V (abs max). |
| 3 | VIN | power_in | Input voltage supply pin (4.5 V to 28 V operating; 30 V abs max). Drain terminal of the high-side power NFET. Bypass with a local ceramic capacitor to GND. |
| 4 | FB | input | Converter feedback input to the error amplifier. Connect to the output voltage through a resistor divider; internal reference VFB = 0.596 V (typ). |
| 5 | EN | input | Enable input. Float (leave open) to enable the converter; pull to GND to disable. Rising threshold 1.21 V (typ), falling 1.19 V (typ); abs max 7 V. |
| 6 | BOOT | power_out | Bootstrap supply for the high-side NFET gate drive circuit. Connect a 0.1-µF ceramic capacitor between BOOT and SW. Abs max BOOT-SW = 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | PMIC |
| Pins | 6 |

## Ordering variants

Same part, different packaging or reel option.

- `TPS54202DDCR`

## CAD (KiCad official)

- Symbol: `TPS54202DDCR`, Adom style from adom-symbol (Input, Output and Ground groups); `tps54202ddcr-outline.kicad_sym` adds the 3D chip outline in its body
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `tps54202ddcr-etched.step` / `tps54202ddcr-etched.glb` carry the MPN as a flat white laser mark on the top, in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps54202ddcr.step` / `tps54202ddcr.glb` are the bare package body.

## Downloads

Two symbols and two STEP files. The STEP files have the same geometry and a different body top:

| File | Size | Use it when |
|---|---|---|
| [`tps54202ddcr.kicad_sym`](tps54202ddcr.kicad_sym) | 3 KB | You want the plain KiCad symbol (the page default). |
| [`tps54202ddcr-outline.kicad_sym`](tps54202ddcr-outline.kicad_sym) | 26 KB | You want the symbol with the 3D chip outline. |
| [`tps54202ddcr.step`](tps54202ddcr.step) | 97 KB | You want the bare part, or you mark your own boards. |
| [`tps54202ddcr-etched.step`](tps54202ddcr-etched.step) | 0.7 MB | You want the part with `TPS54202DDCR` already on it. |

The marking in the etched file is a flat white laser mark: thin faces on the body top in their own
`Adom.LaserEtch` group, coloured white, not raised or recessed lettering. It runs along the package's
2.9 mm length, parallel to the pin rows, as large as fits beside the pin-1 dot, reading from the pin-1 dot end:
upright and left to right with pins 1 to 3 toward you, the same marking the board models and the outline symbol use. It
survives export and drops straight into KiCad or Fusion; hide the group for a bare top.

## Symbol options

The default symbol, `tps54202ddcr.kicad_sym` (the one in the Symbol & Footprint panel), is the plain standard symbol. `tps54202ddcr-outline.kicad_sym` is the same symbol with the part's 3D chip outline added, its part number upright and left to right exactly as on the 3D model. Other layouts can be generated and downloaded here:

::adom-symbol-variants{src="/adom/tps54202ddcr/render/page.json" mpn="TPS54202DDCR"}

## Chip outline

The outline symbol carries the chip's own 3D outline in its body, drawn from the STEP by Adom's OpenCascade
service, with the part number placed exactly where the etched model has it. The outline shows the chip in
the standard iso pose, pins 1 to 3 and the pin-1 dot toward the viewer, so the part number reads upright
and left to right along the package's length, as on a real part. The same outlines are cached here for reuse in other symbols and libraries:

::adom-chip-thumbnail{src="/adom/tps54202ddcr/render/artwork/TPS54202DDCR-thumbs.json"}

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps54202ddcr.pdf) (28 pp, sha256 `a7f9b762dcd5e18e`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps54202ddcr-datasheet.pdf)